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a7a5854f1c
can in 32-bit mode we can choose to optionally *use* 64-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28824 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
3.5 KiB
TableGen
87 lines
3.5 KiB
TableGen
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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//
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def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
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"Enable 64-bit instructions">;
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
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"Enable 64-bit registers usage for ppc32 [beta]">;
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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"Enable Altivec instructions">;
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def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
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"Enable GPUL instructions">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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"Enable the fsqrt instruction">;
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PPCRegisterInfo.td"
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include "PPCSchedule.td"
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include "PPCInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// PowerPC processors supported.
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//
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def : Processor<"generic", G3Itineraries, []>;
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def : Processor<"601", G3Itineraries, []>;
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def : Processor<"602", G3Itineraries, []>;
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def : Processor<"603", G3Itineraries, []>;
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def : Processor<"603e", G3Itineraries, []>;
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def : Processor<"603ev", G3Itineraries, []>;
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def : Processor<"604", G3Itineraries, []>;
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def : Processor<"604e", G3Itineraries, []>;
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def : Processor<"620", G3Itineraries, []>;
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def : Processor<"g3", G3Itineraries, []>;
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def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
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def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
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def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
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def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
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def : Processor<"750", G3Itineraries, []>;
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def : Processor<"970", G5Itineraries,
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[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"g5", G5Itineraries,
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[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def PPCInstrInfo : InstrInfo {
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the PPCInstrInfo.h file.
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let TSFlagsFields = ["PPC970_First",
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"PPC970_Single",
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"PPC970_Cracked",
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"PPC970_Unit"];
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let TSFlagsShifts = [0, 1, 2, 3];
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let isLittleEndianEncoding = 1;
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}
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def PPC : Target {
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// Information about the instructions.
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let InstructionSet = PPCInstrInfo;
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}
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