mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
242 lines
5.4 KiB
LLVM
242 lines
5.4 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_eq_imm
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; CHECK: cmp w0, #31
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; CHECK-NEXT: cset w0, eq
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%cmp = icmp eq i32 %a, 31
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_eq_neg_imm
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; CHECK: cmn w0, #7
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; CHECK-NEXT: cset w0, eq
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%cmp = icmp eq i32 %a, -7
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_eq_i32(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_eq_i32
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, eq
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%cmp = icmp eq i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_ne
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, ne
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%cmp = icmp ne i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_eq_ptr(i8* %a) {
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entry:
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; CHECK-LABEL: icmp_eq_ptr
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; CHECK: cmp x0, #0
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; CHECK-NEXT: cset {{.+}}, eq
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%cmp = icmp eq i8* %a, null
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ne_ptr(i8* %a) {
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entry:
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; CHECK-LABEL: icmp_ne_ptr
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; CHECK: cmp x0, #0
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; CHECK-NEXT: cset {{.+}}, ne
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%cmp = icmp ne i8* %a, null
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_ugt
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, hi
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%cmp = icmp ugt i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_uge
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, hs
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%cmp = icmp uge i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_ult
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, lo
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%cmp = icmp ult i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_ule
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, ls
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%cmp = icmp ule i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_sgt
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, gt
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%cmp = icmp sgt i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_sge
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, ge
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%cmp = icmp sge i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_slt
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, lt
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%cmp = icmp slt i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_sle
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; CHECK: cmp w0, w1
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; CHECK-NEXT: cset w0, le
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%cmp = icmp sle i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_i64
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; CHECK: cmp x0, x1
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; CHECK-NEXT: cset w{{[0-9]+}}, le
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%cmp = icmp sle i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_eq_i16
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; CHECK: sxth w0, w0
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; CHECK: cmp w0, w1, sxth
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; CHECK-NEXT: cset w0, eq
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%cmp = icmp eq i16 %a, %b
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ret i1 %cmp
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}
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define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: icmp_eq_i8
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; CHECK: sxtb w0, w0
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; CHECK-NEXT: cmp w0, w1, sxtb
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; CHECK-NEXT: cset w0, eq
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%cmp = icmp eq i8 %a, %b
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ret i1 %cmp
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}
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define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {
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entry:
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; CHECK-LABEL: icmp_i16_unsigned
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; CHECK: uxth w0, w0
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; CHECK-NEXT: cmp w0, w1, uxth
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; CHECK-NEXT: cset w0, lo
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%cmp = icmp ult i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {
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entry:
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; CHECK-LABEL: icmp_i8_signed
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; CHECK: sxtb w0, w0
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; CHECK-NEXT: cmp w0, w1, sxtb
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; CHECK-NEXT: cset w0, gt
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%cmp = icmp sgt i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i1_signed(i1 %a, i1 %b) nounwind {
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entry:
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; CHECK-LABEL: icmp_i1_signed
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; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1
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; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1
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; CHECK-NEXT: cmp [[REG1]], [[REG2]]
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; CHECK-NEXT: cset w0, gt
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%cmp = icmp sgt i1 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i16_signed_const(i16 %a) nounwind {
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entry:
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; CHECK-LABEL: icmp_i16_signed_const
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; CHECK: sxth w0, w0
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; CHECK-NEXT: cmn w0, #233
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: and w0, w0, #0x1
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%cmp = icmp slt i16 %a, -233
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i8_signed_const(i8 %a) nounwind {
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entry:
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; CHECK-LABEL: icmp_i8_signed_const
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; CHECK: sxtb w0, w0
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; CHECK-NEXT: cmp w0, #124
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; CHECK-NEXT: cset w0, gt
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; CHECK-NEXT: and w0, w0, #0x1
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%cmp = icmp sgt i8 %a, 124
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i1_unsigned_const(i1 %a) nounwind {
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entry:
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; CHECK-LABEL: icmp_i1_unsigned_const
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; CHECK: and w0, w0, #0x1
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: and w0, w0, #0x1
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%cmp = icmp ult i1 %a, 0
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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