mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
271 lines
7.6 KiB
LLVM
271 lines
7.6 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
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%0 = type { i64, i64 }
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define i128 @f0(i8* %p) nounwind readonly {
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; CHECK-LABEL: f0:
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; CHECK: ldxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
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entry:
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%ldrexd = tail call %0 @llvm.aarch64.ldxp(i8* %p)
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%0 = extractvalue %0 %ldrexd, 1
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%1 = extractvalue %0 %ldrexd, 0
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%2 = zext i64 %0 to i128
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%3 = zext i64 %1 to i128
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%shl = shl nuw i128 %2, 64
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%4 = or i128 %shl, %3
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ret i128 %4
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}
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define i32 @f1(i8* %ptr, i128 %val) nounwind {
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; CHECK-LABEL: f1:
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; CHECK: stxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
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entry:
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%tmp4 = trunc i128 %val to i64
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%tmp6 = lshr i128 %val, 64
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%tmp7 = trunc i128 %tmp6 to i64
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%strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
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ret i32 %strexd
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}
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declare %0 @llvm.aarch64.ldxp(i8*) nounwind
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declare i32 @llvm.aarch64.stxp(i64, i64, i8*) nounwind
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@var = global i64 0, align 8
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define void @test_load_i8(i8* %addr) {
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; CHECK-LABEL: test_load_i8:
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; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
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%shortval = trunc i64 %val to i8
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%extval = zext i8 %shortval to i64
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store i64 %extval, i64* @var, align 8
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ret void
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}
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define void @test_load_i16(i16* %addr) {
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; CHECK-LABEL: test_load_i16:
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; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
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; CHECK-NOT: uxth
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
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%shortval = trunc i64 %val to i16
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%extval = zext i16 %shortval to i64
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store i64 %extval, i64* @var, align 8
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ret void
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}
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define void @test_load_i32(i32* %addr) {
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; CHECK-LABEL: test_load_i32:
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; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
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; CHECK-NOT: uxtw
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
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%shortval = trunc i64 %val to i32
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%extval = zext i32 %shortval to i64
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store i64 %extval, i64* @var, align 8
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ret void
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}
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define void @test_load_i64(i64* %addr) {
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; CHECK-LABEL: test_load_i64:
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; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
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store i64 %val, i64* @var, align 8
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ret void
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}
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declare i64 @llvm.aarch64.ldxr.p0i8(i8*) nounwind
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declare i64 @llvm.aarch64.ldxr.p0i16(i16*) nounwind
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declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
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declare i64 @llvm.aarch64.ldxr.p0i64(i64*) nounwind
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define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
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; CHECK-LABEL: test_store_i8:
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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; CHECK: stxrb w0, w1, [x2]
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%extval = zext i8 %val to i64
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%res = call i32 @llvm.aarch64.stxr.p0i8(i64 %extval, i8* %addr)
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ret i32 %res
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}
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define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
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; CHECK-LABEL: test_store_i16:
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; CHECK-NOT: uxth
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; CHECK-NOT: and
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; CHECK: stxrh w0, w1, [x2]
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%extval = zext i16 %val to i64
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%res = call i32 @llvm.aarch64.stxr.p0i16(i64 %extval, i16* %addr)
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ret i32 %res
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}
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define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
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; CHECK-LABEL: test_store_i32:
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; CHECK-NOT: uxtw
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; CHECK-NOT: and
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; CHECK: stxr w0, w1, [x2]
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%extval = zext i32 %val to i64
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%res = call i32 @llvm.aarch64.stxr.p0i32(i64 %extval, i32* %addr)
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ret i32 %res
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}
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define i32 @test_store_i64(i32, i64 %val, i64* %addr) {
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; CHECK-LABEL: test_store_i64:
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; CHECK: stxr w0, x1, [x2]
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%res = call i32 @llvm.aarch64.stxr.p0i64(i64 %val, i64* %addr)
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ret i32 %res
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}
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declare i32 @llvm.aarch64.stxr.p0i8(i64, i8*) nounwind
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declare i32 @llvm.aarch64.stxr.p0i16(i64, i16*) nounwind
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declare i32 @llvm.aarch64.stxr.p0i32(i64, i32*) nounwind
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declare i32 @llvm.aarch64.stxr.p0i64(i64, i64*) nounwind
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; CHECK: test_clear:
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; CHECK: clrex
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define void @test_clear() {
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call void @llvm.aarch64.clrex()
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ret void
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}
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declare void @llvm.aarch64.clrex() nounwind
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define i128 @test_load_acquire_i128(i8* %p) nounwind readonly {
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; CHECK-LABEL: test_load_acquire_i128:
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; CHECK: ldaxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
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entry:
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%ldrexd = tail call %0 @llvm.aarch64.ldaxp(i8* %p)
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%0 = extractvalue %0 %ldrexd, 1
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%1 = extractvalue %0 %ldrexd, 0
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%2 = zext i64 %0 to i128
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%3 = zext i64 %1 to i128
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%shl = shl nuw i128 %2, 64
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%4 = or i128 %shl, %3
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ret i128 %4
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}
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define i32 @test_store_release_i128(i8* %ptr, i128 %val) nounwind {
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; CHECK-LABEL: test_store_release_i128:
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; CHECK: stlxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
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entry:
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%tmp4 = trunc i128 %val to i64
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%tmp6 = lshr i128 %val, 64
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%tmp7 = trunc i128 %tmp6 to i64
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%strexd = tail call i32 @llvm.aarch64.stlxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
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ret i32 %strexd
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}
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declare %0 @llvm.aarch64.ldaxp(i8*) nounwind
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declare i32 @llvm.aarch64.stlxp(i64, i64, i8*) nounwind
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define void @test_load_acquire_i8(i8* %addr) {
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; CHECK-LABEL: test_load_acquire_i8:
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; CHECK: ldaxrb w[[LOADVAL:[0-9]+]], [x0]
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
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%shortval = trunc i64 %val to i8
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%extval = zext i8 %shortval to i64
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store i64 %extval, i64* @var, align 8
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ret void
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}
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define void @test_load_acquire_i16(i16* %addr) {
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; CHECK-LABEL: test_load_acquire_i16:
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; CHECK: ldaxrh w[[LOADVAL:[0-9]+]], [x0]
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; CHECK-NOT: uxth
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
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%shortval = trunc i64 %val to i16
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%extval = zext i16 %shortval to i64
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store i64 %extval, i64* @var, align 8
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ret void
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}
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define void @test_load_acquire_i32(i32* %addr) {
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; CHECK-LABEL: test_load_acquire_i32:
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; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
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; CHECK-NOT: uxtw
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; CHECK-NOT: and
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
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%shortval = trunc i64 %val to i32
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%extval = zext i32 %shortval to i64
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store i64 %extval, i64* @var, align 8
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ret void
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}
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define void @test_load_acquire_i64(i64* %addr) {
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; CHECK-LABEL: test_load_acquire_i64:
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; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
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; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
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%val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
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store i64 %val, i64* @var, align 8
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ret void
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}
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declare i64 @llvm.aarch64.ldaxr.p0i8(i8*) nounwind
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declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
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declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
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declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
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define i32 @test_store_release_i8(i32, i8 %val, i8* %addr) {
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; CHECK-LABEL: test_store_release_i8:
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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; CHECK: stlxrb w0, w1, [x2]
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%extval = zext i8 %val to i64
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%res = call i32 @llvm.aarch64.stlxr.p0i8(i64 %extval, i8* %addr)
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ret i32 %res
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}
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define i32 @test_store_release_i16(i32, i16 %val, i16* %addr) {
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; CHECK-LABEL: test_store_release_i16:
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; CHECK-NOT: uxth
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; CHECK-NOT: and
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; CHECK: stlxrh w0, w1, [x2]
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%extval = zext i16 %val to i64
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%res = call i32 @llvm.aarch64.stlxr.p0i16(i64 %extval, i16* %addr)
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ret i32 %res
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}
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define i32 @test_store_release_i32(i32, i32 %val, i32* %addr) {
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; CHECK-LABEL: test_store_release_i32:
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; CHECK-NOT: uxtw
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; CHECK-NOT: and
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; CHECK: stlxr w0, w1, [x2]
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%extval = zext i32 %val to i64
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%res = call i32 @llvm.aarch64.stlxr.p0i32(i64 %extval, i32* %addr)
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ret i32 %res
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}
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define i32 @test_store_release_i64(i32, i64 %val, i64* %addr) {
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; CHECK-LABEL: test_store_release_i64:
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; CHECK: stlxr w0, x1, [x2]
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%res = call i32 @llvm.aarch64.stlxr.p0i64(i64 %val, i64* %addr)
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ret i32 %res
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}
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declare i32 @llvm.aarch64.stlxr.p0i8(i64, i8*) nounwind
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declare i32 @llvm.aarch64.stlxr.p0i16(i64, i16*) nounwind
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declare i32 @llvm.aarch64.stlxr.p0i32(i64, i32*) nounwind
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declare i32 @llvm.aarch64.stlxr.p0i64(i64, i64*) nounwind
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