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https://github.com/c64scene-ar/llvm-6502.git
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c40dab2069
When the constant divisor was larger than 32bits, then the optimized code generated for the AArch64 backend would emit the wrong code, because the shift was defined as a shift of a 32bit constant '(1<<Lg2(divisor))' and we would loose the upper 32bits. This fixes rdar://problem/18678801. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219934 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
1.5 KiB
LLVM
75 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1
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; CHECK: add w8, w0, #7
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: asr w0, w8, #3
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%div = sdiv i32 %x, 8
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ret i32 %div
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2
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; CHECK: add w8, w0, #7
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: neg w0, w8, asr #3
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%div = sdiv i32 %x, -8
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ret i32 %div
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3
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; CHECK: add w8, w0, #31
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; CHECK: cmp w0, #0
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; CHECK: csel w8, w8, w0, lt
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; CHECK: asr w0, w8, #5
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%div = sdiv i32 %x, 32
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ret i32 %div
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}
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define i64 @test4(i64 %x) {
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; CHECK-LABEL: test4
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; CHECK: add x8, x0, #7
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #3
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%div = sdiv i64 %x, 8
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ret i64 %div
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}
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define i64 @test5(i64 %x) {
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; CHECK-LABEL: test5
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; CHECK: add x8, x0, #7
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: neg x0, x8, asr #3
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%div = sdiv i64 %x, -8
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ret i64 %div
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}
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define i64 @test6(i64 %x) {
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; CHECK-LABEL: test6
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; CHECK: add x8, x0, #63
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #6
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%div = sdiv i64 %x, 64
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ret i64 %div
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}
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define i64 @test7(i64 %x) {
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; CHECK-LABEL: test7
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; CHECK: orr [[REG:x[0-9]+]], xzr, #0xffffffffffff
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; CHECK: add x8, x0, [[REG]]
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; CHECK: cmp x0, #0
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; CHECK: csel x8, x8, x0, lt
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; CHECK: asr x0, x8, #48
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%div = sdiv i64 %x, 281474976710656
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ret i64 %div
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}
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