llvm-6502/test/CodeGen/Hexagon/opt-fneg.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

27 lines
686 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Optimize fneg to togglebit in V5.
define float @foo(float %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
%x.addr = alloca float, align 4
store float %x, float* %x.addr, align 4
%0 = load float, float* %x.addr, align 4
%sub = fsub float -0.000000e+00, %0
ret float %sub
}
define float @bar(float %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
%sub = fsub float -0.000000e+00, %x
ret float %sub
}
define float @baz(float %x) nounwind {
entry:
; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31)
%conv1 = fmul float %x, -1.000000e+00
ret float %conv1
}