mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
280 lines
6.6 KiB
LLVM
280 lines
6.6 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define zeroext i32 @bs4(i32 zeroext %a) #0 {
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entry:
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%0 = tail call i32 @llvm.bswap.i32(i32 %a)
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ret i32 %0
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; CHECK-LABEL: @bs4
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; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
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; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
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; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
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; CHECK: mr 3, [[REG1]]
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; CHECK: blr
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}
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define i64 @bs8(i64 %x) #0 {
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entry:
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%0 = tail call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %0
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; CHECK-LABEL: @bs8
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; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16
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; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
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; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24
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; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
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; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32
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; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
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; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48
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; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
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; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56
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; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
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; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
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; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
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; CHECK: mr 3, [[REG2]]
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; CHECK: blr
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}
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define i64 @test1(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = lshr i64 %i1, 8
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%and = and i64 %0, 5963776000
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ret i64 %and
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; CHECK-LABEL: @test1
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; CHECK-DAG: li [[REG1:[0-9]+]], 11375
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; CHECK-DAG: rotldi [[REG3:[0-9]+]], 4, 56
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; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
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; CHECK: and 3, [[REG3]], [[REG2]]
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; CHECK: blr
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}
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define i64 @test2(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = lshr i64 %i1, 6
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%and = and i64 %0, 133434808670355456
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ret i64 %and
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; CHECK-LABEL: @test2
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; CHECK-DAG: lis [[REG1:[0-9]+]], 474
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; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 58
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648
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; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
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; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
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; CHECK: and 3, [[REG5]], [[REG4]]
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; CHECK: blr
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}
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define i64 @test3(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = shl i64 %i0, 34
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%and = and i64 %0, 191795733152661504
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ret i64 %and
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; CHECK-LABEL: @test3
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; CHECK-DAG: lis [[REG1:[0-9]+]], 170
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; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 34
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861
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; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34
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; CHECK: and 3, [[REG4]], [[REG3]]
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; CHECK: blr
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}
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define i64 @test4(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = lshr i64 %i1, 15
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%and = and i64 %0, 58195968
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ret i64 %and
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; CHECK-LABEL: @test4
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; CHECK: rotldi [[REG1:[0-9]+]], 4, 49
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; CHECK: andis. 3, [[REG1]], 888
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; CHECK: blr
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}
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define i64 @test5(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = shl i64 %i1, 12
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%and = and i64 %0, 127252959854592
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ret i64 %and
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; CHECK-LABEL: @test5
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; CHECK-DAG: lis [[REG1:[0-9]+]], 3703
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; CHECK-DAG: rotldi [[REG4:[0-9]+]], 4, 12
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951
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; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
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; CHECK: and 3, [[REG4]], [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i32 @test6(i32 zeroext %x) #0 {
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entry:
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%and = lshr i32 %x, 16
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%shr = and i32 %and, 255
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%and1 = shl i32 %x, 16
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%shl = and i32 %and1, 16711680
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%or = or i32 %shr, %shl
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ret i32 %or
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; CHECK-LABEL: @test6
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; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31
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; CHECK: rlwimi [[REG1]], 3, 16, 8, 15
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; CHECK: mr 3, [[REG1]]
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; CHECK: blr
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}
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define i64 @test7(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = lshr i64 %i0, 5
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%and = and i64 %0, 58195968
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ret i64 %and
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; CHECK-LABEL: @test7
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; CHECK: rlwinm [[REG1:[0-9]+]], 3, 27, 9, 12
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; CHECK: rlwimi [[REG1]], 3, 27, 6, 7
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; CHECK: mr 3, [[REG1]]
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; CHECK: blr
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}
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define i64 @test8(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = lshr i64 %i0, 1
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%and = and i64 %0, 169172533248
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ret i64 %and
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; CHECK-LABEL: @test8
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; CHECK-DAG: lis [[REG1:[0-9]+]], 4
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; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 63
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527
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; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19
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; CHECK: and 3, [[REG4]], [[REG3]]
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; CHECK: blr
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}
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define i64 @test9(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = lshr i64 %i1, 14
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%and = and i64 %0, 18848677888
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%1 = shl i64 %i1, 51
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%and3 = and i64 %1, 405323966463344640
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%or4 = or i64 %and, %and3
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ret i64 %or4
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; CHECK-LABEL: @test9
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; CHECK-DAG: lis [[REG1:[0-9]+]], 1440
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; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62
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; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
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; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0
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; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
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; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
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; CHECK: and 3, [[REG6]], [[REG4]]
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; CHECK: blr
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}
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define i64 @test10(i64 %i0, i64 %i1) #0 {
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entry:
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%0 = shl i64 %i0, 37
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%and = and i64 %0, 15881483390550016
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%1 = shl i64 %i0, 25
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%and3 = and i64 %1, 2473599172608
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%or4 = or i64 %and, %and3
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ret i64 %or4
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; CHECK-LABEL: @test10
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; CHECK-DAG: lis [[REG1:[0-9]+]], 1
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; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 25
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; CHECK-DAG: rotldi [[REG7:[0-9]+]], 3, 37
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183
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; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017
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; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25
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; CHECK-DAG: sldi [[REG5:[0-9]+]], [[REG3]], 37
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; CHECK-DAG: and [[REG8:[0-9]+]], [[REG6]], [[REG4]]
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; CHECK-DAG: and [[REG9:[0-9]+]], [[REG7]], [[REG5]]
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; CHECK: or 3, [[REG9]], [[REG8]]
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; CHECK: blr
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}
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define i64 @test11(i64 %x) #0 {
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entry:
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%and = and i64 %x, 4294967295
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%shl = shl i64 %x, 32
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%or = or i64 %and, %shl
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ret i64 %or
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; CHECK-LABEL: @test11
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; CHECK: rlwinm 3, 3, 0, 1, 0
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; CHECK: blr
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}
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define i64 @test12(i64 %x) #0 {
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entry:
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%and = and i64 %x, 4294905855
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%shl = shl i64 %x, 32
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%or = or i64 %and, %shl
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ret i64 %or
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; CHECK-LABEL: @test12
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; CHECK: rlwinm 3, 3, 0, 20, 15
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; CHECK: blr
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}
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define i64 @test13(i64 %x) #0 {
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entry:
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%shl = shl i64 %x, 4
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%and = and i64 %shl, 240
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%shr = lshr i64 %x, 28
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%and1 = and i64 %shr, 15
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%or = or i64 %and, %and1
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ret i64 %or
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; CHECK-LABEL: @test13
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; CHECK: rlwinm 3, 3, 4, 24, 31
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; CHECK: blr
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}
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define i64 @test14(i64 %x) #0 {
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entry:
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%shl = shl i64 %x, 4
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%and = and i64 %shl, 240
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%shr = lshr i64 %x, 28
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%and1 = and i64 %shr, 15
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%and2 = and i64 %x, -4294967296
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%or = or i64 %and1, %and2
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%or3 = or i64 %or, %and
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ret i64 %or3
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; CHECK-LABEL: @test14
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; CHECK: rldicr [[REG1:[0-9]+]], 3, 0, 31
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; CHECK: rlwimi [[REG1]], 3, 4, 24, 31
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; CHECK: mr 3, [[REG1]]
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; CHECK: blr
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}
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define i64 @test15(i64 %x) #0 {
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entry:
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%shl = shl i64 %x, 4
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%and = and i64 %shl, 240
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%shr = lshr i64 %x, 28
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%and1 = and i64 %shr, 15
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%and2 = and i64 %x, -256
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%or = or i64 %and1, %and2
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%or3 = or i64 %or, %and
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ret i64 %or3
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; CHECK-LABEL: @test15
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; CHECK: rlwimi 3, 3, 4, 24, 31
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.bswap.i32(i32) #0
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declare i64 @llvm.bswap.i64(i64) #0
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attributes #0 = { nounwind readnone }
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