mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e03aac601f
When using Altivec, we can use vector loads and stores for aligned memcpy and friends. Starting with the P7 and VXS, we have reasonable unaligned vector stores. Starting with the P8, we have fast unaligned loads too. For QPX, we use vector loads are stores, but only for aligned memory accesses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230788 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
2.4 KiB
LLVM
111 lines
2.4 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PWR7
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; RUN: llc -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PWR8
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; RUN: llc -mcpu=a2q < %s | FileCheck %s -check-prefix=A2Q
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define void @foo1(double* nocapture %x, double* nocapture readonly %y) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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%1 = bitcast double* %y to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 32, i32 8, i1 false)
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ret void
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; PWR7-LABEL: @foo1
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; PWR7-NOT: bl memcpy
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; PWR7: ld {{[0-9]+}}, {{[0-9]+}}(4)
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; PWR7: std {{[0-9]+}}, {{[0-9]+}}(3)
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; PWR7: blr
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; PWR8-LABEL: @foo1
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; PWR8: lxvw4x
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @foo1
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; A2Q-NOT: bl memcpy
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; A2Q: ld {{[0-9]+}}, {{[0-9]+}}(4)
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; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
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; A2Q: blr
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}
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; Function Attrs: nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
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; Function Attrs: nounwind
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define void @foo2(double* nocapture %x, double* nocapture readonly %y) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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%1 = bitcast double* %y to i8*
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tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 128, i32 8, i1 false)
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ret void
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; PWR7-LABEL: @foo2
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; PWR7: bl memcpy
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; PWR7: blr
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; PWR8-LABEL: @foo2
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; PWR8: lxvw4x
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @foo2
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; A2Q-NOT: bl memcpy
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; A2Q: ld {{[0-9]+}}, {{[0-9]+}}(4)
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; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
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; A2Q: blr
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}
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; Function Attrs: nounwind
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define void @bar1(double* nocapture %x) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 128, i32 8, i1 false)
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ret void
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; PWR7-LABEL: @bar1
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; PWR7-NOT: bl memset
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; PWR7: stxvw4x
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; PWR7: blr
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; PWR8-LABEL: @bar1
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; PWR8-NOT: bl memset
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @bar1
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; A2Q-NOT: bl memset
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; A2Q: std {{[0-9]+}}, {{[0-9]+}}(3)
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; A2Q: blr
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}
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; Function Attrs: nounwind
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define void @bar2(double* nocapture %x) #0 {
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entry:
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%0 = bitcast double* %x to i8*
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tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 128, i32 32, i1 false)
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ret void
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; PWR7-LABEL: @bar2
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; PWR7-NOT: bl memset
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; PWR7: stxvw4x
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; PWR7: blr
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; PWR8-LABEL: @bar2
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; PWR8-NOT: bl memset
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; PWR8: stxvw4x
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; PWR8: blr
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; A2Q-LABEL: @bar2
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; A2Q-NOT: bl memset
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; A2Q: qvstfdx
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; A2Q: blr
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}
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; Function Attrs: nounwind
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0
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attributes #0 = { nounwind }
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