mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
337 lines
8.7 KiB
LLVM
337 lines
8.7 KiB
LLVM
; RUN: llc < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec -mattr=-vsx | FileCheck %s
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; RUN: llc < %s -march=ppc64le -mattr=+altivec -mattr=-vsx | FileCheck %s
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; Currently VSX support is disabled for this test because we generate lxsdx
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; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we
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; have reg+imm addressing, and is on the list of things to be fixed.
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; The second run step is to ensure that -march=ppc64le is adequate to select
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; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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;
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; Verify use of registers for float/vector aggregate return.
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;
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define [8 x float] @return_float([8 x float] %x) {
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entry:
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ret [8 x float] %x
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}
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; CHECK-LABEL: @return_float
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; CHECK: %entry
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; CHECK-NEXT: blr
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define [8 x double] @return_double([8 x double] %x) {
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entry:
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ret [8 x double] %x
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}
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; CHECK-LABEL: @return_double
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; CHECK: %entry
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; CHECK-NEXT: blr
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define [4 x ppc_fp128] @return_ppcf128([4 x ppc_fp128] %x) {
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entry:
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ret [4 x ppc_fp128] %x
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}
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; CHECK-LABEL: @return_ppcf128
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; CHECK: %entry
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; CHECK-NEXT: blr
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define [8 x <4 x i32>] @return_v4i32([8 x <4 x i32>] %x) {
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entry:
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ret [8 x <4 x i32>] %x
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}
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; CHECK-LABEL: @return_v4i32
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; CHECK: %entry
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; CHECK-NEXT: blr
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;
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; Verify amount of space taken up by aggregates in the parameter save area.
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;
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define i64 @callee_float([7 x float] %a, [7 x float] %b, i64 %c) {
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entry:
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ret i64 %c
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}
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; CHECK-LABEL: @callee_float
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; CHECK: ld 3, 96(1)
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; CHECK: blr
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define void @caller_float(i64 %x, [7 x float] %y) {
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entry:
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tail call void @test_float([7 x float] %y, [7 x float] %y, i64 %x)
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ret void
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}
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; CHECK-LABEL: @caller_float
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; CHECK: std 3, 96(1)
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; CHECK: bl test_float
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declare void @test_float([7 x float], [7 x float], i64)
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define i64 @callee_double(i64 %a, [7 x double] %b, i64 %c) {
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entry:
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ret i64 %c
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}
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; CHECK-LABEL: @callee_double
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; CHECK: ld 3, 96(1)
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; CHECK: blr
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define void @caller_double(i64 %x, [7 x double] %y) {
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entry:
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tail call void @test_double(i64 %x, [7 x double] %y, i64 %x)
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ret void
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}
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; CHECK-LABEL: @caller_double
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; CHECK: std 3, 96(1)
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; CHECK: bl test_double
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declare void @test_double(i64, [7 x double], i64)
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define i64 @callee_ppcf128(i64 %a, [4 x ppc_fp128] %b, i64 %c) {
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entry:
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ret i64 %c
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}
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; CHECK-LABEL: @callee_ppcf128
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; CHECK: ld 3, 104(1)
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; CHECK: blr
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define void @caller_ppcf128(i64 %x, [4 x ppc_fp128] %y) {
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entry:
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tail call void @test_ppcf128(i64 %x, [4 x ppc_fp128] %y, i64 %x)
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ret void
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}
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; CHECK-LABEL: @caller_ppcf128
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; CHECK: std 3, 104(1)
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; CHECK: bl test_ppcf128
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declare void @test_ppcf128(i64, [4 x ppc_fp128], i64)
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define i64 @callee_i64(i64 %a, [7 x i64] %b, i64 %c) {
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entry:
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ret i64 %c
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}
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; CHECK-LABEL: @callee_i64
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; CHECK: ld 3, 96(1)
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; CHECK: blr
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define void @caller_i64(i64 %x, [7 x i64] %y) {
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entry:
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tail call void @test_i64(i64 %x, [7 x i64] %y, i64 %x)
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ret void
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}
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; CHECK-LABEL: @caller_i64
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; CHECK: std 3, 96(1)
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; CHECK: bl test_i64
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declare void @test_i64(i64, [7 x i64], i64)
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define i64 @callee_i128(i64 %a, [4 x i128] %b, i64 %c) {
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entry:
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ret i64 %c
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}
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; CHECK-LABEL: @callee_i128
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; CHECK: ld 3, 112(1)
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; CHECK: blr
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define void @caller_i128(i64 %x, [4 x i128] %y) {
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entry:
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tail call void @test_i128(i64 %x, [4 x i128] %y, i64 %x)
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ret void
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}
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; CHECK-LABEL: @caller_i128
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; CHECK: std 3, 112(1)
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; CHECK: bl test_i128
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declare void @test_i128(i64, [4 x i128], i64)
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define i64 @callee_v4i32(i64 %a, [4 x <4 x i32>] %b, i64 %c) {
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entry:
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ret i64 %c
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}
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; CHECK-LABEL: @callee_v4i32
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; CHECK: ld 3, 112(1)
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; CHECK: blr
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define void @caller_v4i32(i64 %x, [4 x <4 x i32>] %y) {
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entry:
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tail call void @test_v4i32(i64 %x, [4 x <4 x i32>] %y, i64 %x)
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ret void
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}
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; CHECK-LABEL: @caller_v4i32
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; CHECK: std 3, 112(1)
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; CHECK: bl test_v4i32
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declare void @test_v4i32(i64, [4 x <4 x i32>], i64)
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;
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; Verify handling of floating point arguments in GPRs
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;
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%struct.float8 = type { [8 x float] }
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%struct.float5 = type { [5 x float] }
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%struct.float2 = type { [2 x float] }
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@g8 = common global %struct.float8 zeroinitializer, align 4
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@g5 = common global %struct.float5 zeroinitializer, align 4
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@g2 = common global %struct.float2 zeroinitializer, align 4
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define float @callee0([7 x float] %a, [7 x float] %b) {
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entry:
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%b.extract = extractvalue [7 x float] %b, 6
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ret float %b.extract
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}
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; CHECK-LABEL: @callee0
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; CHECK: stw 10, [[OFF:.*]](1)
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; CHECK: lfs 1, [[OFF]](1)
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; CHECK: blr
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define void @caller0([7 x float] %a) {
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entry:
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tail call void @test0([7 x float] %a, [7 x float] %a)
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ret void
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}
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; CHECK-LABEL: @caller0
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; CHECK-DAG: fmr 8, 1
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; CHECK-DAG: fmr 9, 2
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; CHECK-DAG: fmr 10, 3
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; CHECK-DAG: fmr 11, 4
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; CHECK-DAG: fmr 12, 5
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; CHECK-DAG: fmr 13, 6
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; CHECK-DAG: stfs 7, [[OFF:[0-9]+]](1)
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; CHECK-DAG: lwz 10, [[OFF]](1)
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; CHECK: bl test0
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declare void @test0([7 x float], [7 x float])
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define float @callee1([8 x float] %a, [8 x float] %b) {
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entry:
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%b.extract = extractvalue [8 x float] %b, 7
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ret float %b.extract
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}
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; CHECK-LABEL: @callee1
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; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32
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; CHECK: stw [[REG]], [[OFF:.*]](1)
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; CHECK: lfs 1, [[OFF]](1)
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; CHECK: blr
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define void @caller1([8 x float] %a) {
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entry:
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tail call void @test1([8 x float] %a, [8 x float] %a)
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ret void
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}
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; CHECK-LABEL: @caller1
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; CHECK-DAG: fmr 9, 1
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; CHECK-DAG: fmr 10, 2
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; CHECK-DAG: fmr 11, 3
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; CHECK-DAG: fmr 12, 4
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; CHECK-DAG: fmr 13, 5
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; CHECK-DAG: stfs 5, [[OFF0:[0-9]+]](1)
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; CHECK-DAG: stfs 6, [[OFF1:[0-9]+]](1)
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; CHECK-DAG: stfs 7, [[OFF2:[0-9]+]](1)
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; CHECK-DAG: stfs 8, [[OFF3:[0-9]+]](1)
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; CHECK-DAG: lwz [[REG0:[0-9]+]], [[OFF0]](1)
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; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1)
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; CHECK-DAG: lwz [[REG2:[0-9]+]], [[OFF2]](1)
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; CHECK-DAG: lwz [[REG3:[0-9]+]], [[OFF3]](1)
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; CHECK-DAG: sldi [[REG1]], [[REG1]], 32
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; CHECK-DAG: sldi [[REG3]], [[REG3]], 32
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; CHECK-DAG: or 9, [[REG0]], [[REG1]]
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; CHECK-DAG: or 10, [[REG2]], [[REG3]]
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; CHECK: bl test1
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declare void @test1([8 x float], [8 x float])
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define float @callee2([8 x float] %a, [5 x float] %b, [2 x float] %c) {
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entry:
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%c.extract = extractvalue [2 x float] %c, 1
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ret float %c.extract
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}
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; CHECK-LABEL: @callee2
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; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32
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; CHECK: stw [[REG]], [[OFF:.*]](1)
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; CHECK: lfs 1, [[OFF]](1)
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; CHECK: blr
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define void @caller2() {
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entry:
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%0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
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%1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
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%2 = load [2 x float], [2 x float]* getelementptr inbounds (%struct.float2, %struct.float2* @g2, i64 0, i32 0), align 4
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tail call void @test2([8 x float] %0, [5 x float] %1, [2 x float] %2)
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ret void
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}
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; CHECK-LABEL: @caller2
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; CHECK: ld {{[0-9]+}}, .LC
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; CHECK-DAG: lfs 1, 0({{[0-9]+}})
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; CHECK-DAG: lfs 2, 4({{[0-9]+}})
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; CHECK-DAG: lfs 3, 8({{[0-9]+}})
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; CHECK-DAG: lfs 4, 12({{[0-9]+}})
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; CHECK-DAG: lfs 5, 16({{[0-9]+}})
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; CHECK-DAG: lfs 6, 20({{[0-9]+}})
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; CHECK-DAG: lfs 7, 24({{[0-9]+}})
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; CHECK-DAG: lfs 8, 28({{[0-9]+}})
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; CHECK-DAG: lfs 9, 0({{[0-9]+}})
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; CHECK-DAG: lfs 10, 4({{[0-9]+}})
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; CHECK-DAG: lfs 11, 8({{[0-9]+}})
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; CHECK-DAG: lfs 12, 12({{[0-9]+}})
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; CHECK-DAG: lfs 13, 16({{[0-9]+}})
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; CHECK-DAG: lwz [[REG0:[0-9]+]], 0({{[0-9]+}})
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; CHECK-DAG: lwz [[REG1:[0-9]+]], 4({{[0-9]+}})
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; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 32
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; CHECK-DAG: or 10, [[REG0]], [[REG2]]
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; CHECK: bl test2
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declare void @test2([8 x float], [5 x float], [2 x float])
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define double @callee3([8 x float] %a, [5 x float] %b, double %c) {
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entry:
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ret double %c
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}
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; CHECK-LABEL: @callee3
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; CHECK: std 10, [[OFF:.*]](1)
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; CHECK: lfd 1, [[OFF]](1)
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; CHECK: blr
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define void @caller3(double %d) {
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entry:
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%0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
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%1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
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tail call void @test3([8 x float] %0, [5 x float] %1, double %d)
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ret void
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}
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; CHECK-LABEL: @caller3
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; CHECK: stfd 1, [[OFF:.*]](1)
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; CHECK: ld 10, [[OFF]](1)
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; CHECK: bl test3
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declare void @test3([8 x float], [5 x float], double)
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define float @callee4([8 x float] %a, [5 x float] %b, float %c) {
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entry:
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ret float %c
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}
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; CHECK-LABEL: @callee4
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; CHECK: stw 10, [[OFF:.*]](1)
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; CHECK: lfs 1, [[OFF]](1)
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; CHECK: blr
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define void @caller4(float %f) {
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entry:
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%0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
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%1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
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tail call void @test4([8 x float] %0, [5 x float] %1, float %f)
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ret void
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}
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; CHECK-LABEL: @caller4
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; CHECK: stfs 1, [[OFF:.*]](1)
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; CHECK: lwz 10, [[OFF]](1)
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; CHECK: bl test4
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declare void @test4([8 x float], [5 x float], float)
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