llvm-6502/test/CodeGen/PowerPC/rs-undef-use.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

49 lines
1.6 KiB
LLVM

; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
target triple = "powerpc64-unknown-linux-gnu"
define void @autogen_SD156869(i8*, i64*) {
BB:
%A3 = alloca <2 x i1>
%A2 = alloca <8 x i32>
br label %CF
CF: ; preds = %CF85, %CF, %BB
br i1 undef, label %CF, label %CF82.critedge
CF82.critedge: ; preds = %CF
store i8 -59, i8* %0
br label %CF82
CF82: ; preds = %CF82, %CF82.critedge
%L17 = load i8, i8* %0
%E18 = extractelement <2 x i64> undef, i32 0
%PC = bitcast <2 x i1>* %A3 to i64*
br i1 undef, label %CF82, label %CF84.critedge
CF84.critedge: ; preds = %CF82
store i64 455385, i64* %PC
br label %CF84
CF84: ; preds = %CF84, %CF84.critedge
%L40 = load i64, i64* %PC
store i64 -1, i64* %PC
%Sl46 = select i1 undef, i1 undef, i1 false
br i1 %Sl46, label %CF84, label %CF85
CF85: ; preds = %CF84
%L47 = load i64, i64* %PC
store i64 %E18, i64* %PC
%PC52 = bitcast <8 x i32>* %A2 to ppc_fp128*
store ppc_fp128 0xM4D436562A0416DE00000000000000000, ppc_fp128* %PC52
%PC59 = bitcast i64* %1 to i8*
%Cmp61 = icmp slt i64 %L47, %L40
br i1 %Cmp61, label %CF, label %CF77
CF77: ; preds = %CF77, %CF85
br i1 undef, label %CF77, label %CF81
CF81: ; preds = %CF77
store i8 %L17, i8* %PC59
ret void
}