mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
207 lines
5.9 KiB
LLVM
207 lines
5.9 KiB
LLVM
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-32 %s
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; RUN: llc -mtriple=powerpc-unknown-linux-gnu -disable-fp-elim -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-32-PIC %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.s = type { i32, i32 }
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declare void @bar(i32*)
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@barbaz = external global i32
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define void @goo(%struct.s* byval nocapture readonly %a) {
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entry:
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%x = alloca [2 x i32], align 32
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%a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
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%0 = load i32, i32* %a1, align 4
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%arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
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store i32 %0, i32* %arrayidx, align 32
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%b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
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%1 = load i32, i32* %b, align 4
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%2 = load i32, i32* @barbaz, align 4
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%arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
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store i32 %2, i32* %arrayidx2, align 4
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call void @bar(i32* %arrayidx)
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ret void
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}
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; CHECK-LABEL: @goo
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; CHECK-DAG: mflr 0
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; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
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; CHECK-DAG: std 30, -16(1)
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; CHECK-DAG: mr 30, 1
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; CHECK-DAG: std 0, 16(1)
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; CHECK-DAG: subfic 0, [[REG]], -160
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; CHECK: stdux 1, 1, 0
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; CHECK: .cfi_def_cfa_register r30
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; CHECK: .cfi_offset r30, -16
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; CHECK: .cfi_offset lr, 16
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; CHECK: std 3, 48(30)
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; CHECK: ld 1, 0(1)
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; CHECK-DAG: ld 0, 16(1)
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; CHECK-DAG: ld 30, -16(1)
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; CHECK-DAG: mtlr 0
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; CHECK: blr
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; CHECK-FP-LABEL: @goo
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; CHECK-FP-DAG: mflr 0
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; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
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; CHECK-FP-DAG: std 31, -8(1)
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; CHECK-FP-DAG: std 30, -16(1)
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; CHECK-FP-DAG: mr 30, 1
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; CHECK-FP-DAG: std 0, 16(1)
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; CHECK-FP-DAG: subfic 0, [[REG]], -160
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; CHECK-FP: stdux 1, 1, 0
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; CHECK-FP: .cfi_def_cfa_register r30
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; CHECK-FP: .cfi_offset r31, -8
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; CHECK-FP: .cfi_offset r30, -16
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; CHECK-FP: .cfi_offset lr, 16
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; CHECK-FP: mr 31, 1
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; CHECK-FP: std 3, 48(30)
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; CHECK-FP: ld 1, 0(1)
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; CHECK-FP-DAG: ld 0, 16(1)
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; CHECK-FP-DAG: ld 31, -8(1)
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; CHECK-FP-DAG: ld 30, -16(1)
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; CHECK-FP-DAG: mtlr 0
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; CHECK-FP: blr
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; CHECK-32-LABEL: @goo
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; CHECK-32-DAG: mflr 0
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; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
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; CHECK-32-DAG: stw 30, -8(1)
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; CHECK-32-DAG: mr 30, 1
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; CHECK-32-DAG: stw 0, 4(1)
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; CHECK-32-DAG: subfic 0, [[REG]], -64
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; CHECK-32: stwux 1, 1, 0
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; CHECK-32-PIC-LABEL: @goo
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; CHECK-32-PIC-DAG: mflr 0
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; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
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; CHECK-32-PIC-DAG: stw 29, -12(1)
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; CHECK-32-PIC-DAG: mr 29, 1
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; CHECK-32-PIC-DAG: stw 0, 4(1)
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; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
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; CHECK-32-PIC: stwux 1, 1, 0
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; The large-frame-size case.
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define void @hoo(%struct.s* byval nocapture readonly %a) {
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entry:
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%x = alloca [200000 x i32], align 32
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%a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
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%0 = load i32, i32* %a1, align 4
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%arrayidx = getelementptr inbounds [200000 x i32], [200000 x i32]* %x, i64 0, i64 0
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store i32 %0, i32* %arrayidx, align 32
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%b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
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%1 = load i32, i32* %b, align 4
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%arrayidx2 = getelementptr inbounds [200000 x i32], [200000 x i32]* %x, i64 0, i64 1
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store i32 %1, i32* %arrayidx2, align 4
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call void @bar(i32* %arrayidx)
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ret void
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}
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; CHECK-LABEL: @hoo
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; CHECK-DAG: lis [[REG1:[0-9]+]], -13
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; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59
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; CHECK-DAG: mflr 0
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; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
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; CHECK-DAG: std 30, -16(1)
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; CHECK-DAG: mr 30, 1
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; CHECK-DAG: std 0, 16(1)
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; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
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; CHECK: stdux 1, 1, 0
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; CHECK: .cfi_def_cfa_register r30
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; CHECK: blr
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; CHECK-32-LABEL: @hoo
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; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
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; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
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; CHECK-32-DAG: mflr 0
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; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
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; CHECK-32-DAG: stw 30, -8(1)
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; CHECK-32-DAG: mr 30, 1
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; CHECK-32-DAG: stw 0, 4(1)
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; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
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; CHECK-32: stwux 1, 1, 0
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; CHECK-32: blr
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; CHECK-32-PIC-LABEL: @hoo
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; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
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; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
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; CHECK-32-PIC-DAG: mflr 0
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; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
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; CHECK-32-PIC-DAG: stw 29, -12(1)
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; CHECK-32-PIC-DAG: mr 29, 1
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; CHECK-32-PIC-DAG: stw 0, 4(1)
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; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
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; CHECK-32: stwux 1, 1, 0
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; CHECK-32: blr
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; Make sure that the FP save area is still allocated correctly relative to
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; where r30 is saved.
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define void @loo(%struct.s* byval nocapture readonly %a) {
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entry:
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%x = alloca [2 x i32], align 32
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%a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0
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%0 = load i32, i32* %a1, align 4
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%arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 0
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store i32 %0, i32* %arrayidx, align 32
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%b = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 1
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%1 = load i32, i32* %b, align 4
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%arrayidx2 = getelementptr inbounds [2 x i32], [2 x i32]* %x, i64 0, i64 1
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store i32 %1, i32* %arrayidx2, align 4
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call void @bar(i32* %arrayidx)
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call void asm sideeffect "", "~{f30}"() nounwind
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ret void
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}
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; CHECK-LABEL: @loo
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; CHECK-DAG: mflr 0
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; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
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; CHECK-DAG: std 30, -32(1)
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; CHECK-DAG: mr 30, 1
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; CHECK-DAG: std 0, 16(1)
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; CHECK-DAG: subfic 0, [[REG]], -192
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; CHECK: stdux 1, 1, 0
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; CHECK: .cfi_def_cfa_register r30
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; CHECK: stfd 30, -16(30)
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; CHECK: blr
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; CHECK-FP-LABEL: @loo
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; CHECK-FP-DAG: mflr 0
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; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59
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; CHECK-FP-DAG: std 31, -24(1)
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; CHECK-FP-DAG: std 30, -32(1)
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; CHECK-FP-DAG: mr 30, 1
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; CHECK-FP-DAG: std 0, 16(1)
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; CHECK-FP-DAG: subfic 0, [[REG]], -192
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; CHECK-FP: stdux 1, 1, 0
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; CHECK-FP: .cfi_def_cfa_register r30
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; CHECK-FP: stfd 30, -16(30)
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; CHECK-FP: blr
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