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https://github.com/c64scene-ar/llvm-6502.git
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1c4b6de5ed
When enabling PPC64LE, I disabled some optimizations of BUILD_VECTOR nodes for little endian because wrong results were produced. I've subsequently investigated and found this is due to a call to BuildVectorSDNode::isConstantSplat that was always specifying big-endian. With this changed to correctly identify the target endianness, the optimizations work as expected. I found another case of a call to the same method with big-endian hardcoded, in PPC::isAllNegativeZeroVector(). I discovered this was an orphaned method with no callers, so I've just removed it. The existing test/CodeGen/PowerPC/vec_constants.ll checks these optimizations, so for testing I've just added a variant for little endian. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234011 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
2.6 KiB
LLVM
85 lines
2.6 KiB
LLVM
; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
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%tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1]
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%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1]
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store <4 x i32> %tmp4, <4 x i32>* %P1
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%tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1]
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%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
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store <4 x i32> %tmp9, <4 x i32>* %P2
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%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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%tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1]
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%tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp13, <4 x float>* %P3
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ret void
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; CHECK-LABEL: test1:
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; CHECK-NOT: CPI
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}
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define <4 x i32> @test_30() nounwind {
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ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
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; CHECK-LABEL: test_30:
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; CHECK: vspltisw
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; CHECK-NEXT: vadduwm
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; CHECK-NEXT: blr
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}
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define <4 x i32> @test_29() nounwind {
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ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
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; CHECK-LABEL: test_29:
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; CHECK: vspltisw
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; CHECK-NEXT: vspltisw
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; CHECK-NEXT: vsubuwm
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; CHECK-NEXT: blr
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}
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define <8 x i16> @test_n30() nounwind {
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ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
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; CHECK-LABEL: test_n30:
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; CHECK: vspltish
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; CHECK-NEXT: vadduhm
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; CHECK-NEXT: blr
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}
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define <16 x i8> @test_n104() nounwind {
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ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
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; CHECK-LABEL: test_n104:
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; CHECK: vspltisb
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; CHECK-NEXT: vslb
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; CHECK-NEXT: blr
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}
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define <4 x i32> @test_vsldoi() nounwind {
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ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
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; CHECK-LABEL: test_vsldoi:
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; CHECK: vspltisw
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; CHECK-NEXT: vsldoi
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; CHECK-NEXT: blr
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}
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define <8 x i16> @test_vsldoi_65023() nounwind {
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ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
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; CHECK-LABEL: test_vsldoi_65023:
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; CHECK: vspltish
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; CHECK-NEXT: vsldoi
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; CHECK-NEXT: blr
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}
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define <4 x i32> @test_rol() nounwind {
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ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
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; CHECK-LABEL: test_rol:
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; CHECK: vspltisw
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; CHECK-NEXT: vrlw
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; CHECK-NEXT: blr
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}
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