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551a3d7b56
We recently discovered an issue that reinforces what a good idea it is to always specify -mcpu in our code generation tests, particularly for -mattr=+vsx. This patch ensures that all tests that specify -mattr=+vsx also specify -mcpu=pwr7 or -mcpu=pwr8, as appropriate. Some of the uses of -mattr=+vsx added recently don't make much sense (when specified for -mtriple=powerpc-apple-darwin8 or -march=ppc32, for example). For cases like this I've just removed the extra VSX test commands; there's enough coverage without them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220173 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1014 B
LLVM
25 lines
1014 B
LLVM
; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=+vsx -verify-machineinstrs -fast-isel=false -mcpu=pwr7 < %s | FileCheck -check-prefix=CHECK-VSX %s
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; This verifies that we generate correct spill/reload code for vector regs.
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define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
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entry:
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%i.addr = alloca i32, align 4
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%w.addr = alloca <4 x float>, align 16
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store i32 %i, i32* %i.addr, align 4
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store <4 x float> %w, <4 x float>* %w.addr, align 16
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call void @foo(i32* %i.addr)
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ret void
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}
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; CHECK: stvx 2,
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; We would prefer to test for "stxvw4x 34," but current -O0 code
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; needlessly generates "vor 3,2,2 / stxvw4x 35,0,3", so we'll settle for
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; the opcode.
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; CHECK-VSX: stxvw4x
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declare void @foo(i32*)
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