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https://github.com/c64scene-ar/llvm-6502.git
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59a5e979b5
This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232988 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
2.9 KiB
LLVM
106 lines
2.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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;
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;
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; Most SALU instructions ignore control flow, so we need to make sure
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; they don't overwrite values from other blocks.
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; If the branch decision is made based on a value in an SGPR then all
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; threads will execute the same code paths, so we don't need to worry
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; about instructions in different blocks overwriting each other.
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; SI-LABEL: {{^}}sgpr_if_else_salu_br:
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; SI: s_add
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; SI: s_add
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define void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = add i32 %b, %c
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br label %endif
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else:
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%2 = add i32 %d, %e
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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%4 = add i32 %3, %a
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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; The two S_ADD instructions should write to different registers, since
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; different threads will take different control flow paths.
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; SI-LABEL: {{^}}sgpr_if_else_valu_br:
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; SI: s_add_i32 [[SGPR:s[0-9]+]]
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; SI-NOT: s_add_i32 [[SGPR]]
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define void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%tid_f = uitofp i32 %tid to float
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%tmp1 = fcmp ueq float %tid_f, 0.0
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br i1 %tmp1, label %if, label %else
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if:
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%tmp2 = add i32 %b, %c
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br label %endif
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else:
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%tmp3 = add i32 %d, %e
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br label %endif
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endif:
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%tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Should write to different SGPR pairs instead of copying to
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; VALU for i1 phi.
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; SI-LABEL: {{^}}sgpr_if_else_valu_cmp_phi_br:
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]]
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; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]]
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; SI: BB2_1:
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; SI: buffer_load_dword [[AVAL:v[0-9]+]]
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; SI: v_cmp_eq_i32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]]
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; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]]
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; SI: v_cmp_ne_i32_e32 [[CMP_CMP:vcc]], 0, [[V_CMP]]
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; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP_CMP]]
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; SI: buffer_store_dword [[RESULT]]
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define void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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entry:
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%tmp1 = icmp eq i32 %tid, 0
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br i1 %tmp1, label %if, label %else
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if:
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%gep.if = getelementptr i32, i32 addrspace(1)* %a, i32 %tid
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%a.val = load i32, i32 addrspace(1)* %gep.if
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%cmp.if = icmp eq i32 %a.val, 0
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br label %endif
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else:
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%gep.else = getelementptr i32, i32 addrspace(1)* %b, i32 %tid
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%b.val = load i32, i32 addrspace(1)* %gep.else
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%cmp.else = icmp slt i32 %b.val, 0
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br label %endif
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endif:
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%tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
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%ext = sext i1 %tmp4 to i32
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #0
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attributes #0 = { readnone }
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