llvm-6502/test/CodeGen/Thumb/dyn-stackalloc.ll
David Blaikie 5a70dd1d82 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator
Similar to gep (r230786) and load (r230794) changes.

Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.

(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)

import fileinput
import sys
import re

rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)

def conv(match):
  line = match.group(1)
  line += match.group(4)
  line += ", "
  line += match.group(2)
  return line

line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
  sys.stdout.write(line[off:match.start()])
  sys.stdout.write(conv(match))
  off = match.end()
sys.stdout.write(line[off:])

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-13 18:20:45 +00:00

79 lines
2.6 KiB
LLVM

; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_GREEDY
; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=RA_BASIC
%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
define void @t1(%struct.state* %v) {
; CHECK-LABEL: t1:
; CHECK: push
; CHECK: add r7, sp, #12
; CHECK: lsls r[[R0:[0-9]+]]
; CHECK: mov r[[R1:[0-9]+]], sp
; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r[[R0]]
; CHECK: mov sp, r[[R2]]
%tmp6 = load i32, i32* null
%tmp8 = alloca float, i32 %tmp6
store i32 1, i32* null
br i1 false, label %bb123.preheader, label %return
bb123.preheader:
br i1 false, label %bb43, label %return
bb43:
call fastcc void @f1( float* %tmp8, float* null, i32 0 )
%tmp70 = load i32, i32* null
%tmp85 = getelementptr float, float* %tmp8, i32 0
call fastcc void @f2( float* null, float* null, float* %tmp85, i32 %tmp70 )
ret void
return:
ret void
}
declare fastcc void @f1(float*, float*, i32)
declare fastcc void @f2(float*, float*, float*, i32)
%struct.comment = type { i8**, i32*, i32, i8* }
@str215 = external global [2 x i8]
define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
; CHECK-LABEL: t2:
; CHECK: push
; CHECK: add r7, sp, #12
; CHECK: sub sp, #
; CHECK: mov r[[R0:[0-9]+]], sp
; CHECK: str r{{[0-9+]}}, [r[[R0]]
; RA_GREEDY: str r{{[0-9+]}}, [r[[R0]]
; RA_BASIC: stm r[[R0]]!
; CHECK-NOT: ldr r0, [sp
; CHECK: mov r[[R1:[0-9]+]], sp
; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r{{[0-9]+}}
; CHECK: mov sp, r[[R2]]
; CHECK-NOT: ldr r0, [sp
; CHECK: bx
%tmp1 = call i32 @strlen( i8* %tag )
%tmp3 = call i32 @strlen( i8* %contents )
%tmp4 = add i32 %tmp1, 2
%tmp5 = add i32 %tmp4, %tmp3
%tmp6 = alloca i8, i32 %tmp5
%tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag )
%tmp6.len = call i32 @strlen( i8* %tmp6 )
%tmp6.indexed = getelementptr i8, i8* %tmp6, i32 %tmp6.len
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false)
%tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents )
call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 )
ret void
}
declare i32 @strlen(i8*)
declare i8* @strcat(i8*, i8*)
declare fastcc void @comment_add(%struct.comment*, i8*)
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
declare i8* @strcpy(i8*, i8*)