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Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.9 KiB
C++
79 lines
2.9 KiB
C++
//===- BlackfinISelLowering.h - Blackfin DAG Lowering Interface -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Blackfin uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef BLACKFIN_ISELLOWERING_H
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#define BLACKFIN_ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "Blackfin.h"
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namespace llvm {
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namespace BFISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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CALL, // A call instruction.
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RET_FLAG, // Return with a flag operand.
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Wrapper // Address wrapper
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};
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}
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class BlackfinTargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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public:
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BlackfinTargetLowering(TargetMachine &TM);
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virtual MVT getSetCCResultType(MVT VT) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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const char *getTargetNodeName(unsigned Opcode) const;
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unsigned getFunctionAlignment(const Function *F) const;
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private:
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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SDValue LowerADDE(SDValue Op, SelectionDAG &DAG);
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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unsigned CallConv, bool isVarArg, bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerReturn(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG);
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};
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} // end namespace llvm
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#endif // BLACKFIN_ISELLOWERING_H
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