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f462e3fac7
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
3.0 KiB
C++
104 lines
3.0 KiB
C++
//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate information gleaned from the
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// target register and register class definitions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_REGISTERS_H
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#define CODEGEN_REGISTERS_H
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/DenseMap.h"
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#include <string>
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#include <vector>
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#include <set>
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#include <cstdlib>
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namespace llvm {
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class Record;
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/// CodeGenRegister - Represents a register definition.
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struct CodeGenRegister {
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Record *TheDef;
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const std::string &getName() const;
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unsigned EnumValue;
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unsigned CostPerUse;
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CodeGenRegister(Record *R);
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};
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struct CodeGenRegisterClass {
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Record *TheDef;
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std::string Namespace;
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std::vector<Record*> Elements;
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std::vector<MVT::SimpleValueType> VTs;
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unsigned SpillSize;
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unsigned SpillAlignment;
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int CopyCost;
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bool Allocatable;
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// Map SubRegIndex -> RegisterClass
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DenseMap<Record*,Record*> SubRegClasses;
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std::string MethodProtos, MethodBodies;
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const std::string &getName() const;
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const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
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unsigned getNumValueTypes() const { return VTs.size(); }
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MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
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if (VTNum < VTs.size())
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return VTs[VTNum];
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assert(0 && "VTNum greater than number of ValueTypes in RegClass!");
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abort();
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}
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bool containsRegister(Record *R) const {
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for (unsigned i = 0, e = Elements.size(); i != e; ++i)
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if (Elements[i] == R) return true;
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return false;
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}
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// Returns true if RC is a strict subclass.
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// RC is a sub-class of this class if it is a valid replacement for any
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// instruction operand where a register of this classis required. It must
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// satisfy these conditions:
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//
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// 1. All RC registers are also in this.
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// 2. The RC spill size must not be smaller than our spill size.
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// 3. RC spill alignment must be compatible with ours.
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//
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bool hasSubClass(const CodeGenRegisterClass *RC) const {
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if (RC->Elements.size() > Elements.size() ||
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(SpillAlignment && RC->SpillAlignment % SpillAlignment) ||
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SpillSize > RC->SpillSize)
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return false;
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std::set<Record*> RegSet;
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for (unsigned i = 0, e = Elements.size(); i != e; ++i) {
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Record *Reg = Elements[i];
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RegSet.insert(Reg);
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}
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for (unsigned i = 0, e = RC->Elements.size(); i != e; ++i) {
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Record *Reg = RC->Elements[i];
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if (!RegSet.count(Reg))
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return false;
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}
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return true;
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}
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CodeGenRegisterClass(Record *R);
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};
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}
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#endif
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