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6b9d461780
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
415 lines
15 KiB
C++
415 lines
15 KiB
C++
//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16InstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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static cl::opt<bool> NeverUseSaveRestore(
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"mips16-never-use-save-restore",
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cl::init(false),
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cl::desc("For testing ability to adjust stack pointer "
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"without save/restore instruction"),
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cl::Hidden);
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Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm, Mips::BimmX16),
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RI(*tm.getSubtargetImpl(), *this) {}
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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return RI;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned Mips16InstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned Mips16InstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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return 0;
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}
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void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.contains(DestReg) &&
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Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::MoveR3216;
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else if (Mips::CPURegsRegClass.contains(DestReg) &&
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Mips::CPU16RegsRegClass.contains(SrcReg))
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Opc = Mips::Move32R16;
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else if ((SrcReg == Mips::HI) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mfhi16, SrcReg = 0;
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else if ((SrcReg == Mips::LO) &&
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(Mips::CPU16RegsRegClass.contains(DestReg)))
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Opc = Mips::Mflo16, SrcReg = 0;
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void Mips16InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::SwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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}
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void Mips16InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
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Opc = Mips::LwRxSpImmX16;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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}
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bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock &MBB = *MI->getParent();
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switch(MI->getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA16:
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ExpandRetRA16(MBB, MI, Mips::JrcRa16);
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
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case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
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case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
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case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
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case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
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case Mips::BtnezX16: return Mips::BteqzX16;
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case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
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case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
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case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
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case Mips::BteqzX16: return Mips::BtnezX16;
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case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
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case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
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case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
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case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
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case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
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case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
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}
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assert(false && "Implement this function.");
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return 0;
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}
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// Adjust SP by FrameSize bytes. Save RA, S0, S1
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void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (!NeverUseSaveRestore) {
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if (isUInt<11>(FrameSize))
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BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
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else {
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int Base = 2040; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
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if (isInt<16>(-Remainder))
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BuildAddiuSpImm(MBB, I, DL, -Remainder);
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else
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adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
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}
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}
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else {
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//
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// sw ra, -4[sp]
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// sw s1, -8[sp]
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// sw s0, -12[sp]
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
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Mips::RA);
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MIB1.addReg(Mips::SP);
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MIB1.addImm(-4);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
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Mips::S1);
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MIB2.addReg(Mips::SP);
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MIB2.addImm(-8);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
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Mips::S0);
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MIB3.addReg(Mips::SP);
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MIB3.addImm(-12);
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adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
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}
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}
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// Adjust SP by FrameSize bytes. Restore RA, S0, S1
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void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (!NeverUseSaveRestore) {
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if (isUInt<11>(FrameSize))
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BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
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else {
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int Base = 2040; // should create template function like isUInt that
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// returns largest possible n bit unsigned integer
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int64_t Remainder = FrameSize - Base;
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if (isInt<16>(Remainder))
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BuildAddiuSpImm(MBB, I, DL, Remainder);
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else
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adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
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BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
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}
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}
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else {
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adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
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// lw ra, -4[sp]
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// lw s1, -8[sp]
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// lw s0, -12[sp]
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
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Mips::A0);
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MIB1.addReg(Mips::SP);
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MIB1.addImm(-4);
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MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
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Mips::RA);
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MIB0.addReg(Mips::A0);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
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Mips::S1);
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MIB2.addReg(Mips::SP);
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MIB2.addImm(-8);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
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Mips::S0);
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MIB3.addReg(Mips::SP);
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MIB3.addImm(-12);
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}
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}
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// Adjust SP by Amount bytes where bytes can be up to 32bit number.
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// This can only be called at times that we know that there is at least one free
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// register.
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// This is clearly safe at prologue and epilogue.
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//
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void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Reg1, unsigned Reg2) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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// MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
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// unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
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// unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
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//
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// li reg1, constant
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// move reg2, sp
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// add reg1, reg1, reg2
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// move sp, reg1
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//
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//
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MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
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MIB1.addImm(Amount);
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MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
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MIB2.addReg(Mips::SP, RegState::Kill);
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MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
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MIB3.addReg(Reg1);
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MIB3.addReg(Reg2, RegState::Kill);
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MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
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Mips::SP);
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MIB4.addReg(Reg1, RegState::Kill);
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}
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void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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assert(false && "adjust stack pointer amount exceeded");
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}
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/// Adjust SP by Amount bytes.
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void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
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BuildAddiuSpImm(MBB, I, DL, Amount);
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else
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adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
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}
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/// This function generates the sequence of instructions needed to get the
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/// result of adding register REG and immediate IMM.
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unsigned
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Mips16InstrInfo::loadImmediate(unsigned FrameReg,
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int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned &NewImm) const {
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//
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// given original instruction is:
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// Instr rx, T[offset] where offset is too big.
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//
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// lo = offset & 0xFFFF
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// hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
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//
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// let T = temporary register
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// li T, hi
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// shl T, 16
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// add T, Rx, T
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//
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RegScavenger rs;
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int32_t lo = Imm & 0xFFFF;
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int32_t hi = ((Imm >> 16) + (lo >> 15)) & 0xFFFF;
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NewImm = lo;
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unsigned Reg =0;
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unsigned SpReg = 0;
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rs.enterBasicBlock(&MBB);
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rs.forward(II);
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//
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// we use T0 for the first register, if we need to save something away.
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// we use T1 for the second register, if we need to save something away.
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//
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unsigned FirstRegSaved =0, SecondRegSaved=0;
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unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
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Reg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
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if (Reg == 0) {
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FirstRegSaved = Reg = Mips::V0;
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FirstRegSavedTo = Mips::T0;
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copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
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}
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else
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rs.setUsed(Reg);
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BuildMI(MBB, II, DL, get(Mips::LiRxImmX16), Reg).addImm(hi);
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BuildMI(MBB, II, DL, get(Mips::SllX16), Reg).addReg(Reg).
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addImm(16);
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if (FrameReg == Mips::SP) {
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SpReg = rs.FindUnusedReg(&Mips::CPU16RegsRegClass);
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if (SpReg == 0) {
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if (Reg != Mips::V1) {
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SecondRegSaved = SpReg = Mips::V1;
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SecondRegSavedTo = Mips::T1;
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}
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else {
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SecondRegSaved = SpReg = Mips::V0;
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SecondRegSavedTo = Mips::T0;
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}
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copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
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}
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else
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rs.setUsed(SpReg);
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copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg)
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.addReg(Reg);
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}
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else
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BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
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.addReg(Reg, RegState::Kill);
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if (FirstRegSaved || SecondRegSaved) {
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II = llvm::next(II);
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if (FirstRegSaved)
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copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
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if (SecondRegSaved)
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copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
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}
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return Reg;
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}
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unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
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return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
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Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
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Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
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Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
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Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
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Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
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Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
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Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
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Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
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}
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void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opc) const {
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BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
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}
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void Mips16InstrInfo::BuildAddiuSpImm(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL, int64_t Imm) const {
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if (validSpImm8(Imm))
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BuildMI(MBB, II, DL, get(Mips::AddiuSpImm16)).addImm(Imm);
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else
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BuildMI(MBB, II, DL, get(Mips::AddiuSpImmX16)).addImm(Imm);
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}
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const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
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return new Mips16InstrInfo(TM);
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}
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