mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
6b9d461780
if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
4.8 KiB
C++
123 lines
4.8 KiB
C++
//===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Mips16 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef MIPS16INSTRUCTIONINFO_H
|
|
#define MIPS16INSTRUCTIONINFO_H
|
|
|
|
#include "Mips16RegisterInfo.h"
|
|
#include "MipsInstrInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
class Mips16InstrInfo : public MipsInstrInfo {
|
|
const Mips16RegisterInfo RI;
|
|
|
|
public:
|
|
explicit Mips16InstrInfo(MipsTargetMachine &TM);
|
|
|
|
virtual const MipsRegisterInfo &getRegisterInfo() const;
|
|
|
|
/// isLoadFromStackSlot - If the specified machine instruction is a direct
|
|
/// load from a stack slot, return the virtual or physical register number of
|
|
/// the destination along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than loading from the stack slot.
|
|
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
|
|
int &FrameIndex) const;
|
|
|
|
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
|
/// store to a stack slot, return the virtual or physical register number of
|
|
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than storing to the stack slot.
|
|
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
|
|
int &FrameIndex) const;
|
|
|
|
virtual void copyPhysReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI, DebugLoc DL,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
bool KillSrc) const;
|
|
|
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned DestReg, int FrameIndex,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
|
|
|
|
virtual unsigned GetOppositeBranchOpc(unsigned Opc) const;
|
|
|
|
// Adjust SP by FrameSize bytes. Save RA, S0, S1
|
|
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
// Adjust SP by FrameSize bytes. Restore RA, S0, S1
|
|
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
|
|
/// Adjust SP by Amount bytes.
|
|
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
/// Emit a series of instructions to load an immediate.
|
|
// This is to adjust some FrameReg. We return the new register to be used
|
|
// in place of FrameReg and the adjusted immediate field (&NewImm)
|
|
//
|
|
unsigned loadImmediate(unsigned FrameReg,
|
|
int64_t Imm, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator II, DebugLoc DL,
|
|
unsigned &NewImm) const;
|
|
|
|
static bool validSpImm8(int offset) {
|
|
return ((offset & 7) == 0) && isInt<11>(offset);
|
|
}
|
|
|
|
//
|
|
// build the proper one based on the Imm field
|
|
//
|
|
void BuildAddiuSpImm(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator II, DebugLoc DL,
|
|
int64_t Imm) const;
|
|
|
|
|
|
private:
|
|
virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const;
|
|
|
|
void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned Opc) const;
|
|
|
|
// Adjust SP by Amount bytes where bytes can be up to 32bit number.
|
|
void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned Reg1, unsigned Reg2) const;
|
|
|
|
// Adjust SP by Amount bytes where bytes can be up to 32bit number.
|
|
void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
|
|
};
|
|
|
|
}
|
|
|
|
#endif
|