mirror of
https://github.com/c64scene-ar/llvm-6502.git
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818f609459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160953 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
8.7 KiB
TableGen
174 lines
8.7 KiB
TableGen
//===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the sign and zero extension operations.
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//
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//===----------------------------------------------------------------------===//
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let neverHasSideEffects = 1 in {
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let Defs = [AX], Uses = [AL] in
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def CBW : I<0x98, RawFrm, (outs), (ins),
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"{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
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let Defs = [EAX], Uses = [AX] in
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def CWDE : I<0x98, RawFrm, (outs), (ins),
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"{cwtl|cwde}", []>; // EAX = signext(AX)
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let Defs = [AX,DX], Uses = [AX] in
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def CWD : I<0x99, RawFrm, (outs), (ins),
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"{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
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let Defs = [EAX,EDX], Uses = [EAX] in
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def CDQ : I<0x99, RawFrm, (outs), (ins),
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"{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
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let Defs = [RAX], Uses = [EAX] in
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def CDQE : RI<0x98, RawFrm, (outs), (ins),
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"{cltq|cdqe}", []>; // RAX = signext(EAX)
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let Defs = [RAX,RDX], Uses = [RAX] in
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def CQO : RI<0x99, RawFrm, (outs), (ins),
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"{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
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}
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// Sign/Zero extenders
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let neverHasSideEffects = 1 in {
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def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
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TB, OpSize;
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let mayLoad = 1 in
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def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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"movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>,
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TB, OpSize;
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} // neverHasSideEffects = 1
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def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB;
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def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
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"movs{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB;
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def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
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"movs{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB;
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def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"movs{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>,
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TB;
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let neverHasSideEffects = 1 in {
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def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
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TB, OpSize;
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let mayLoad = 1 in
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def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
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"movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
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TB, OpSize;
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} // neverHasSideEffects = 1
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def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB;
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def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB;
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def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
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"movz{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB;
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def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"movz{wl|x}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>,
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TB;
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// These are the same as the regular MOVZX32rr8 and MOVZX32rm8
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// except that they use GR32_NOREX for the output operand register class
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// instead of GR32. This allows them to operate on h registers on x86-64.
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let neverHasSideEffects = 1, isCodeGenOnly = 1 in {
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def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
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(outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[], IIC_MOVZX>, TB;
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let mayLoad = 1 in
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def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
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(outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
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"movz{bl|x}\t{$src, $dst|$dst, $src}",
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[], IIC_MOVZX>, TB;
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}
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// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
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// operand, which makes it a rare instruction with an 8-bit register
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// operand that can never access an h register. If support for h registers
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// were generalized, this would require a special register class.
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def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
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"movs{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR8:$src))], IIC_MOVSX>, TB;
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def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
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"movs{bq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 addr:$src))], IIC_MOVSX>,
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TB;
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def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"movs{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR16:$src))], IIC_MOVSX>, TB;
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def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movs{wq|x}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i16 addr:$src))], IIC_MOVSX>,
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TB;
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def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>;
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def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
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"movs{lq|xd}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>;
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// movzbq and movzwq encodings for the disassembler
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def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
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TB;
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def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
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"movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
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TB;
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def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
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TB;
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def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
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TB;
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// FIXME: These should be Pat patterns.
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let isCodeGenOnly = 1 in {
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// Use movzbl instead of movzbq when the destination is a register; it's
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// equivalent due to implicit zero-extending, and it has a smaller encoding.
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def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
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"", [(set GR64:$dst, (zext GR8:$src))], IIC_MOVZX>, TB;
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def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
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"", [(set GR64:$dst, (zextloadi64i8 addr:$src))], IIC_MOVZX>,
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TB;
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// Use movzwl instead of movzwq when the destination is a register; it's
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// equivalent due to implicit zero-extending, and it has a smaller encoding.
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def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
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"", [(set GR64:$dst, (zext GR16:$src))], IIC_MOVZX>, TB;
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def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"", [(set GR64:$dst, (zextloadi64i16 addr:$src))],
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IIC_MOVZX>, TB;
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// There's no movzlq instruction, but movl can be used for this purpose, using
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// implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
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// extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
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// zero-extension, however this isn't possible when the 32-bit value is
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// defined by a truncate or is copied from something where the high bits aren't
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// necessarily all zero. In such cases, we fall back to these explicit zext
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// instructions.
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def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
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"", [(set GR64:$dst, (zext GR32:$src))], IIC_MOVZX>;
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def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
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"", [(set GR64:$dst, (zextloadi64i32 addr:$src))],
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IIC_MOVZX>;
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}
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