mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
760 lines
24 KiB
C++
760 lines
24 KiB
C++
//===- ARM64AddressingModes.h - ARM64 Addressing Modes ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM64 addressing mode implementation stuff.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
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#define LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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namespace llvm {
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/// ARM64_AM - ARM64 Addressing Mode Stuff
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namespace ARM64_AM {
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//===----------------------------------------------------------------------===//
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// Shifts
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//
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enum ShiftType {
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InvalidShift = -1,
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LSL = 0,
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LSR = 1,
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ASR = 2,
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ROR = 3,
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MSL = 4
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};
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/// getShiftName - Get the string encoding for the shift type.
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static inline const char *getShiftName(ARM64_AM::ShiftType ST) {
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switch (ST) {
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default: assert(false && "unhandled shift type!");
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case ARM64_AM::LSL: return "lsl";
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case ARM64_AM::LSR: return "lsr";
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case ARM64_AM::ASR: return "asr";
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case ARM64_AM::ROR: return "ror";
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case ARM64_AM::MSL: return "msl";
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}
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return 0;
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}
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/// getShiftType - Extract the shift type.
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static inline ARM64_AM::ShiftType getShiftType(unsigned Imm) {
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return ARM64_AM::ShiftType((Imm >> 6) & 0x7);
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}
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/// getShiftValue - Extract the shift value.
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static inline unsigned getShiftValue(unsigned Imm) {
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return Imm & 0x3f;
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}
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/// getShifterImm - Encode the shift type and amount:
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/// imm: 6-bit shift amount
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/// shifter: 000 ==> lsl
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/// 001 ==> lsr
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/// 010 ==> asr
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/// 011 ==> ror
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/// 100 ==> msl
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/// {8-6} = shifter
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/// {5-0} = imm
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static inline unsigned getShifterImm(ARM64_AM::ShiftType ST, unsigned Imm) {
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assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
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return (unsigned(ST) << 6) | (Imm & 0x3f);
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}
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//===----------------------------------------------------------------------===//
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// Extends
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//
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enum ExtendType {
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InvalidExtend = -1,
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UXTB = 0,
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UXTH = 1,
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UXTW = 2,
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UXTX = 3,
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SXTB = 4,
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SXTH = 5,
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SXTW = 6,
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SXTX = 7
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};
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/// getExtendName - Get the string encoding for the extend type.
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static inline const char *getExtendName(ARM64_AM::ExtendType ET) {
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switch (ET) {
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default: assert(false && "unhandled extend type!");
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case ARM64_AM::UXTB: return "uxtb";
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case ARM64_AM::UXTH: return "uxth";
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case ARM64_AM::UXTW: return "uxtw";
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case ARM64_AM::UXTX: return "uxtx";
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case ARM64_AM::SXTB: return "sxtb";
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case ARM64_AM::SXTH: return "sxth";
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case ARM64_AM::SXTW: return "sxtw";
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case ARM64_AM::SXTX: return "sxtx";
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}
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return 0;
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}
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/// getArithShiftValue - get the arithmetic shift value.
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static inline unsigned getArithShiftValue(unsigned Imm) {
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return Imm & 0x7;
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}
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/// getExtendType - Extract the extend type for operands of arithmetic ops.
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static inline ARM64_AM::ExtendType getArithExtendType(unsigned Imm) {
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return ARM64_AM::ExtendType((Imm >> 3) & 0x7);
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}
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/// getArithExtendImm - Encode the extend type and shift amount for an
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/// arithmetic instruction:
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/// imm: 3-bit extend amount
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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/// {5-3} = shifter
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/// {2-0} = imm3
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static inline unsigned getArithExtendImm(ARM64_AM::ExtendType ET,
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unsigned Imm) {
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assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
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return (unsigned(ET) << 3) | (Imm & 0x7);
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}
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/// getMemDoShift - Extract the "do shift" flag value for load/store
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/// instructions.
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static inline bool getMemDoShift(unsigned Imm) {
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return (Imm & 0x1) != 0;
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}
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/// getExtendType - Extract the extend type for the offset operand of
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/// loads/stores.
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static inline ARM64_AM::ExtendType getMemExtendType(unsigned Imm) {
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return ARM64_AM::ExtendType((Imm >> 1) & 0x7);
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}
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/// getExtendImm - Encode the extend type and amount for a load/store inst:
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/// imm: 3-bit extend amount
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/// shifter: 000 ==> uxtb
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/// 001 ==> uxth
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/// 010 ==> uxtw
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/// 011 ==> uxtx
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/// 100 ==> sxtb
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/// 101 ==> sxth
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/// 110 ==> sxtw
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/// 111 ==> sxtx
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/// {3-1} = shifter
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/// {0} = imm3
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static inline unsigned getMemExtendImm(ARM64_AM::ExtendType ET, bool Imm) {
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assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
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return (unsigned(ET) << 1) | (Imm & 0x7);
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}
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//===----------------------------------------------------------------------===//
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// Prefetch
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//
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/// Pre-fetch operator names.
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/// The enum values match the encoding values:
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/// prfop<4:3> 00=preload data, 10=prepare for store
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/// prfop<2:1> 00=target L1 cache, 01=target L2 cache, 10=target L3 cache,
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/// prfop<0> 0=non-streaming (temporal), 1=streaming (non-temporal)
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enum PrefetchOp {
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InvalidPrefetchOp = -1,
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PLDL1KEEP = 0x00,
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PLDL1STRM = 0x01,
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PLDL2KEEP = 0x02,
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PLDL2STRM = 0x03,
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PLDL3KEEP = 0x04,
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PLDL3STRM = 0x05,
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PSTL1KEEP = 0x10,
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PSTL1STRM = 0x11,
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PSTL2KEEP = 0x12,
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PSTL2STRM = 0x13,
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PSTL3KEEP = 0x14,
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PSTL3STRM = 0x15
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};
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/// isNamedPrefetchOp - Check if the prefetch-op 5-bit value has a name.
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static inline bool isNamedPrefetchOp(unsigned prfop) {
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switch (prfop) {
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default: return false;
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case ARM64_AM::PLDL1KEEP: case ARM64_AM::PLDL1STRM: case ARM64_AM::PLDL2KEEP:
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case ARM64_AM::PLDL2STRM: case ARM64_AM::PLDL3KEEP: case ARM64_AM::PLDL3STRM:
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case ARM64_AM::PSTL1KEEP: case ARM64_AM::PSTL1STRM: case ARM64_AM::PSTL2KEEP:
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case ARM64_AM::PSTL2STRM: case ARM64_AM::PSTL3KEEP: case ARM64_AM::PSTL3STRM:
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return true;
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}
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}
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/// getPrefetchOpName - Get the string encoding for the prefetch operator.
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static inline const char *getPrefetchOpName(ARM64_AM::PrefetchOp prfop) {
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switch (prfop) {
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default: assert(false && "unhandled prefetch-op type!");
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case ARM64_AM::PLDL1KEEP: return "pldl1keep";
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case ARM64_AM::PLDL1STRM: return "pldl1strm";
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case ARM64_AM::PLDL2KEEP: return "pldl2keep";
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case ARM64_AM::PLDL2STRM: return "pldl2strm";
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case ARM64_AM::PLDL3KEEP: return "pldl3keep";
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case ARM64_AM::PLDL3STRM: return "pldl3strm";
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case ARM64_AM::PSTL1KEEP: return "pstl1keep";
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case ARM64_AM::PSTL1STRM: return "pstl1strm";
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case ARM64_AM::PSTL2KEEP: return "pstl2keep";
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case ARM64_AM::PSTL2STRM: return "pstl2strm";
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case ARM64_AM::PSTL3KEEP: return "pstl3keep";
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case ARM64_AM::PSTL3STRM: return "pstl3strm";
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}
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return 0;
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}
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static inline uint64_t ror(uint64_t elt, unsigned size) {
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return ((elt & 1) << (size-1)) | (elt >> 1);
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}
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/// processLogicalImmediate - Determine if an immediate value can be encoded
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/// as the immediate operand of a logical instruction for the given register
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/// size. If so, return true with "encoding" set to the encoded value in
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/// the form N:immr:imms.
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static inline bool processLogicalImmediate(uint64_t imm, unsigned regSize,
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uint64_t &encoding) {
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if (imm == 0ULL || imm == ~0ULL ||
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(regSize != 64 && (imm >> regSize != 0 || imm == ~0U)))
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return false;
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unsigned size = 2;
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uint64_t eltVal = imm;
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// First, determine the element size.
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while (size < regSize) {
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unsigned numElts = regSize / size;
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unsigned mask = (1ULL << size) - 1;
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uint64_t lowestEltVal = imm & mask;
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bool allMatched = true;
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for (unsigned i = 1; i < numElts; ++i) {
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uint64_t currEltVal = (imm >> (i*size)) & mask;
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if (currEltVal != lowestEltVal) {
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allMatched = false;
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break;
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}
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}
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if (allMatched) {
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eltVal = lowestEltVal;
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break;
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}
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size *= 2;
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}
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// Second, determine the rotation to make the element be: 0^m 1^n.
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for (unsigned i = 0; i < size; ++i) {
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eltVal = ror(eltVal, size);
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uint32_t clz = countLeadingZeros(eltVal) - (64 - size);
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uint32_t cto = CountTrailingOnes_64(eltVal);
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if (clz + cto == size) {
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// Encode in immr the number of RORs it would take to get *from* this
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// element value to our target value, where i+1 is the number of RORs
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// to go the opposite direction.
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unsigned immr = size - (i + 1);
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// If size has a 1 in the n'th bit, create a value that has zeroes in
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// bits [0, n] and ones above that.
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uint64_t nimms = ~(size-1) << 1;
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// Or the CTO value into the low bits, which must be below the Nth bit
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// bit mentioned above.
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nimms |= (cto-1);
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// Extract the seventh bit and toggle it to create the N field.
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unsigned N = ((nimms >> 6) & 1) ^ 1;
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encoding = (N << 12) | (immr << 6) | (nimms & 0x3f);
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return true;
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}
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}
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return false;
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}
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/// isLogicalImmediate - Return true if the immediate is valid for a logical
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/// immediate instruction of the given register size. Return false otherwise.
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static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
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uint64_t encoding;
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return processLogicalImmediate(imm, regSize, encoding);
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}
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/// encodeLogicalImmediate - Return the encoded immediate value for a logical
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/// immediate instruction of the given register size.
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static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
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uint64_t encoding = 0;
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bool res = processLogicalImmediate(imm, regSize, encoding);
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assert(res && "invalid logical immediate");
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(void)res;
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return encoding;
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}
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/// decodeLogicalImmediate - Decode a logical immediate value in the form
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/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
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/// integer value it represents with regSize bits.
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static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
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// Extract the N, imms, and immr fields.
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unsigned N = (val >> 12) & 1;
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unsigned immr = (val >> 6) & 0x3f;
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unsigned imms = val & 0x3f;
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assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
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int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
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assert(len >= 0 && "undefined logical immediate encoding");
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unsigned size = (1 << len);
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unsigned R = immr & (size - 1);
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unsigned S = imms & (size - 1);
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assert(S != size - 1 && "undefined logical immediate encoding");
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uint64_t pattern = (1ULL << (S + 1)) - 1;
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for (unsigned i = 0; i < R; ++i)
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pattern = ror(pattern, size);
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// Replicate the pattern to fill the regSize.
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while (size != regSize) {
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pattern |= (pattern << size);
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size *= 2;
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}
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return pattern;
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}
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/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
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/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
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/// is a valid encoding for an integer value with regSize bits.
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static inline bool isValidDecodeLogicalImmediate(uint64_t val,
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unsigned regSize) {
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// Extract the N and imms fields needed for checking.
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unsigned N = (val >> 12) & 1;
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unsigned imms = val & 0x3f;
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if (regSize == 32 && N != 0) // undefined logical immediate encoding
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return false;
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int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
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if (len < 0) // undefined logical immediate encoding
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return false;
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unsigned size = (1 << len);
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unsigned S = imms & (size - 1);
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if (S == size - 1) // undefined logical immediate encoding
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return false;
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Floating-point Immediates
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//
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static inline float getFPImmFloat(unsigned Imm) {
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// We expect an 8-bit binary encoding of a floating-point number here.
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union {
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uint32_t I;
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float F;
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} FPUnion;
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uint8_t Sign = (Imm >> 7) & 0x1;
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uint8_t Exp = (Imm >> 4) & 0x7;
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uint8_t Mantissa = Imm & 0xf;
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// 8-bit FP iEEEE Float Encoding
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// abcd efgh aBbbbbbc defgh000 00000000 00000000
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//
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// where B = NOT(b);
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FPUnion.I = 0;
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FPUnion.I |= Sign << 31;
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FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
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FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
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FPUnion.I |= (Exp & 0x3) << 23;
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FPUnion.I |= Mantissa << 19;
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return FPUnion.F;
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}
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/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
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/// floating-point value. If the value cannot be represented as an 8-bit
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/// floating-point value, then return -1.
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static inline int getFP32Imm(const APInt &Imm) {
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uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
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int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
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int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0x7ffff)
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return -1;
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Mantissa >>= 19;
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if ((Mantissa & 0xf) != Mantissa)
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return -1;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp+3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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static inline int getFP32Imm(const APFloat &FPImm) {
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return getFP32Imm(FPImm.bitcastToAPInt());
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}
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/// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
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/// floating-point value. If the value cannot be represented as an 8-bit
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/// floating-point value, then return -1.
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static inline int getFP64Imm(const APInt &Imm) {
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uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
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int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
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uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
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// We can handle 4 bits of mantissa.
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// mantissa = (16+UInt(e:f:g:h))/16.
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if (Mantissa & 0xffffffffffffULL)
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return -1;
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Mantissa >>= 48;
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if ((Mantissa & 0xf) != Mantissa)
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return -1;
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// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
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if (Exp < -3 || Exp > 4)
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return -1;
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Exp = ((Exp+3) & 0x7) ^ 4;
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return ((int)Sign << 7) | (Exp << 4) | Mantissa;
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}
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static inline int getFP64Imm(const APFloat &FPImm) {
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return getFP64Imm(FPImm.bitcastToAPInt());
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}
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//===--------------------------------------------------------------------===//
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// AdvSIMD Modified Immediates
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//===--------------------------------------------------------------------===//
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// 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
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static inline bool isAdvSIMDModImmType1(uint64_t Imm) {
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return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
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((Imm & 0xffffff00ffffff00ULL) == 0);
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}
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static inline uint8_t encodeAdvSIMDModImmType1(uint64_t Imm) {
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return (Imm & 0xffULL);
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}
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static inline uint64_t decodeAdvSIMDModImmType1(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 32) | EncVal;
|
|
}
|
|
|
|
// 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
|
|
static inline bool isAdvSIMDModImmType2(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0xffff00ffffff00ffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType2(uint64_t Imm) {
|
|
return (Imm & 0xff00ULL) >> 8;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType2(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 40) | (EncVal << 8);
|
|
}
|
|
|
|
// 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
|
|
static inline bool isAdvSIMDModImmType3(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0xff00ffffff00ffffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType3(uint64_t Imm) {
|
|
return (Imm & 0xff0000ULL) >> 16;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType3(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 48) | (EncVal << 16);
|
|
}
|
|
|
|
// abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
|
|
static inline bool isAdvSIMDModImmType4(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0x00ffffff00ffffffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType4(uint64_t Imm) {
|
|
return (Imm & 0xff000000ULL) >> 24;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType4(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 56) | (EncVal << 24);
|
|
}
|
|
|
|
// 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
|
|
static inline bool isAdvSIMDModImmType5(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
(((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
|
|
((Imm & 0xff00ff00ff00ff00ULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType5(uint64_t Imm) {
|
|
return (Imm & 0xffULL);
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType5(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
|
|
}
|
|
|
|
// abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
|
|
static inline bool isAdvSIMDModImmType6(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
(((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
|
|
((Imm & 0x00ff00ff00ff00ffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType6(uint64_t Imm) {
|
|
return (Imm & 0xff00ULL) >> 8;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType6(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
|
|
}
|
|
|
|
// 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
|
|
static inline bool isAdvSIMDModImmType7(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType7(uint64_t Imm) {
|
|
return (Imm & 0xff00ULL) >> 8;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType7(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
|
|
}
|
|
|
|
// 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
|
|
static inline bool isAdvSIMDModImmType8(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType8(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType8(uint64_t Imm) {
|
|
return (Imm & 0x00ff0000ULL) >> 16;
|
|
}
|
|
|
|
// abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
|
|
static inline bool isAdvSIMDModImmType9(uint64_t Imm) {
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
|
|
((Imm >> 56) == (Imm & 0x000000ffULL));
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType9(uint64_t Imm) {
|
|
return (Imm & 0xffULL);
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType9(uint8_t Imm) {
|
|
uint64_t EncVal = Imm;
|
|
EncVal |= (EncVal << 8);
|
|
EncVal |= (EncVal << 16);
|
|
EncVal |= (EncVal << 32);
|
|
return EncVal;
|
|
}
|
|
|
|
// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
|
|
// cmode: 1110, op: 1
|
|
static inline bool isAdvSIMDModImmType10(uint64_t Imm) {
|
|
uint64_t ByteA = Imm & 0xff00000000000000ULL;
|
|
uint64_t ByteB = Imm & 0x00ff000000000000ULL;
|
|
uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
|
|
uint64_t ByteD = Imm & 0x000000ff00000000ULL;
|
|
uint64_t ByteE = Imm & 0x00000000ff000000ULL;
|
|
uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
|
|
uint64_t ByteG = Imm & 0x000000000000ff00ULL;
|
|
uint64_t ByteH = Imm & 0x00000000000000ffULL;
|
|
|
|
return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
|
|
(ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
|
|
(ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
|
|
(ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
|
|
(ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
|
|
(ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
|
|
(ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
|
|
(ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) {
|
|
bool BitA = Imm & 0xff00000000000000ULL;
|
|
bool BitB = Imm & 0x00ff000000000000ULL;
|
|
bool BitC = Imm & 0x0000ff0000000000ULL;
|
|
bool BitD = Imm & 0x000000ff00000000ULL;
|
|
bool BitE = Imm & 0x00000000ff000000ULL;
|
|
bool BitF = Imm & 0x0000000000ff0000ULL;
|
|
bool BitG = Imm & 0x000000000000ff00ULL;
|
|
bool BitH = Imm & 0x00000000000000ffULL;
|
|
|
|
unsigned EncVal = BitA;
|
|
EncVal <<= 1;
|
|
EncVal |= BitB;
|
|
EncVal <<= 1;
|
|
EncVal |= BitC;
|
|
EncVal <<= 1;
|
|
EncVal |= BitD;
|
|
EncVal <<= 1;
|
|
EncVal |= BitE;
|
|
EncVal <<= 1;
|
|
EncVal |= BitF;
|
|
EncVal <<= 1;
|
|
EncVal |= BitG;
|
|
EncVal <<= 1;
|
|
EncVal |= BitH;
|
|
return EncVal;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType10(uint8_t Imm) {
|
|
uint64_t EncVal = 0;
|
|
if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
|
|
if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
|
|
if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
|
|
if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
|
|
if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
|
|
if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
|
|
if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
|
|
if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
|
|
return EncVal;
|
|
}
|
|
|
|
// aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
|
|
static inline bool isAdvSIMDModImmType11(uint64_t Imm) {
|
|
uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
|
|
return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
|
|
(BString == 0x1f || BString == 0x20) &&
|
|
((Imm & 0x0007ffff0007ffffULL) == 0);
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) {
|
|
bool BitA = (Imm & 0x80000000ULL);
|
|
bool BitB = (Imm & 0x20000000ULL);
|
|
bool BitC = (Imm & 0x01000000ULL);
|
|
bool BitD = (Imm & 0x00800000ULL);
|
|
bool BitE = (Imm & 0x00400000ULL);
|
|
bool BitF = (Imm & 0x00200000ULL);
|
|
bool BitG = (Imm & 0x00100000ULL);
|
|
bool BitH = (Imm & 0x00080000ULL);
|
|
|
|
unsigned EncVal = BitA;
|
|
EncVal <<= 1;
|
|
EncVal |= BitB;
|
|
EncVal <<= 1;
|
|
EncVal |= BitC;
|
|
EncVal <<= 1;
|
|
EncVal |= BitD;
|
|
EncVal <<= 1;
|
|
EncVal |= BitE;
|
|
EncVal <<= 1;
|
|
EncVal |= BitF;
|
|
EncVal <<= 1;
|
|
EncVal |= BitG;
|
|
EncVal <<= 1;
|
|
EncVal |= BitH;
|
|
return EncVal;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType11(uint8_t Imm) {
|
|
uint64_t EncVal = 0;
|
|
if (Imm & 0x80) EncVal |= 0x80000000ULL;
|
|
if (Imm & 0x40) EncVal |= 0x3e000000ULL;
|
|
else EncVal |= 0x40000000ULL;
|
|
if (Imm & 0x20) EncVal |= 0x01000000ULL;
|
|
if (Imm & 0x10) EncVal |= 0x00800000ULL;
|
|
if (Imm & 0x08) EncVal |= 0x00400000ULL;
|
|
if (Imm & 0x04) EncVal |= 0x00200000ULL;
|
|
if (Imm & 0x02) EncVal |= 0x00100000ULL;
|
|
if (Imm & 0x01) EncVal |= 0x00080000ULL;
|
|
return (EncVal << 32) | EncVal;
|
|
}
|
|
|
|
// aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
|
|
static inline bool isAdvSIMDModImmType12(uint64_t Imm) {
|
|
uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
|
|
return ((BString == 0xff || BString == 0x100) &&
|
|
((Imm & 0x0000ffffffffffffULL) == 0));
|
|
}
|
|
|
|
static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) {
|
|
bool BitA = (Imm & 0x8000000000000000ULL);
|
|
bool BitB = (Imm & 0x0040000000000000ULL);
|
|
bool BitC = (Imm & 0x0020000000000000ULL);
|
|
bool BitD = (Imm & 0x0010000000000000ULL);
|
|
bool BitE = (Imm & 0x0008000000000000ULL);
|
|
bool BitF = (Imm & 0x0004000000000000ULL);
|
|
bool BitG = (Imm & 0x0002000000000000ULL);
|
|
bool BitH = (Imm & 0x0001000000000000ULL);
|
|
|
|
unsigned EncVal = BitA;
|
|
EncVal <<= 1;
|
|
EncVal |= BitB;
|
|
EncVal <<= 1;
|
|
EncVal |= BitC;
|
|
EncVal <<= 1;
|
|
EncVal |= BitD;
|
|
EncVal <<= 1;
|
|
EncVal |= BitE;
|
|
EncVal <<= 1;
|
|
EncVal |= BitF;
|
|
EncVal <<= 1;
|
|
EncVal |= BitG;
|
|
EncVal <<= 1;
|
|
EncVal |= BitH;
|
|
return EncVal;
|
|
}
|
|
|
|
static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) {
|
|
uint64_t EncVal = 0;
|
|
if (Imm & 0x80) EncVal |= 0x8000000000000000ULL;
|
|
if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL;
|
|
else EncVal |= 0x4000000000000000ULL;
|
|
if (Imm & 0x20) EncVal |= 0x0020000000000000ULL;
|
|
if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;
|
|
if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;
|
|
if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;
|
|
if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;
|
|
if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;
|
|
return (EncVal << 32) | EncVal;
|
|
}
|
|
|
|
} // end namespace ARM64_AM
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|