mirror of
https://github.com/c64scene-ar/llvm-6502.git
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5e3c87ee1a
This adds support for parsing and emitting the SBREL relocation variant for the ARM target. Handling this relocation variant is necessary for supporting the full ARM ELF specification. Addresses PR22128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225595 91177308-0d34-0410-b5e6-96231b3b80d8
38 lines
859 B
ArmAsm
38 lines
859 B
ArmAsm
@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-readobj -r - \
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@ RUN: | FileCheck %s
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@ RUN: llvm-mc -triple thumbv7-eabi -filetype obj -o - %s | llvm-readobj -r - \
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@ RUN: | FileCheck %s
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.syntax unified
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.section .text.r_arm_abs8
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.byte abs8_0 -128
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.byte abs8_1 +255
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@ CHECK: Section {{.*}} .rel.text.r_arm_abs8 {
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@ CHECK: 0x0 R_ARM_ABS8 abs8_0 0x0
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@ CHECK: 0x1 R_ARM_ABS8 abs8_1 0x0
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@ CHECK: }
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.section .text.r_arm_abs16
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.short abs16_0 -32768
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.short abs16_1 +65535
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@ CHECK: Section {{.*}} .rel.text.r_arm_abs16 {
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@ CHECK: 0x0 R_ARM_ABS16 abs16_0 0x0
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@ CHECK: 0x2 R_ARM_ABS16 abs16_1 0x0
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@ CHECK: }
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.section .text.r_arm_sbrel32
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.word target(sbrel)
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.word target(SBREL)
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@ CHECK: Section {{.*}} .rel.text.r_arm_sbrel32 {
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@ CHECK: 0x0 R_ARM_SBREL32 target 0x0
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@ CHECK: 0x4 R_ARM_SBREL32 target 0x0
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@ CHECK: }
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