llvm-6502/ldrd-strd-gnu-sp.s at 7b8defda793c0f22fdccb98232d0ae5230453d6f - llvm-6502 - Applefritter: Git

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Stepan Dyatkovskiy 37e5cfa4aa PR19320:

The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-03 11:29:15 +00:00

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ArmAsm

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 // PR19320
 // RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
 .text
 // CHECK: ldrd	r12, sp, [r0, #32]      @ encoding: [0xd0,0xc2,0xc0,0xe1]
         ldrd    r12, [r0, #32]
 // CHECK: strd	r12, sp, [r0, #32]      @ encoding: [0xf0,0xc2,0xc0,0xe1]
         strd    r12, [r0, #32]