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9bdd785014
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
978 B
ArmAsm
36 lines
978 B
ArmAsm
@ RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
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.text
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add r0, r0, r0
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@ .wibble should *not* inherit .text's mapping symbol. It's a completely different section.
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.section .wibble
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add r0, r0, r0
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@ A section should be able to start with a $t
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.section .starts_thumb
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.thumb
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adds r0, r0, r0
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@ A setion should be able to start with a $d
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.section .starts_data
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.word 42
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@ Changing back to .text should not emit a redundant $a
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.text
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.arm
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add r0, r0, r0
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@ With all those constraints, we want:
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@ + .text to have $a at 0 and no others
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@ + .wibble to have $a at 0
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@ + .starts_thumb to have $t at 0
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@ + .starts_data to have $d at 0
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@ CHECK: 00000000 .text 00000000 $a
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@ CHECK-NEXT: 00000000 .wibble 00000000 $a
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@ CHECK-NEXT: 00000000 .starts_data 00000000 $d
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@ CHECK-NEXT: 00000000 .starts_thumb 00000000 $t
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@ CHECK-NOT: ${{[adt]}}
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