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https://github.com/c64scene-ar/llvm-6502.git
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to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
4.6 KiB
C++
144 lines
4.6 KiB
C++
//===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZRegisterInfo.h"
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#include "SystemZSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#define GET_REGINFO_TARGET_DESC
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#include "SystemZGenRegisterInfo.inc"
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using namespace llvm;
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SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
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const SystemZInstrInfo &tii)
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: SystemZGenRegisterInfo(0), TM(tm), TII(tii) {
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}
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const unsigned*
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SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const unsigned CalleeSavedRegs[] = {
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SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
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SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
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SystemZ::R14D, SystemZ::R15D,
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SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
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SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L,
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0
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};
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return CalleeSavedRegs;
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}
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BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (TFI->hasFP(MF)) {
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// R11D is the frame pointer. Reserve all aliases.
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11W);
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Reserved.set(SystemZ::R10P);
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Reserved.set(SystemZ::R10Q);
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}
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Reserved.set(SystemZ::R14D);
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R14W);
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Reserved.set(SystemZ::R15W);
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Reserved.set(SystemZ::R14P);
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Reserved.set(SystemZ::R14Q);
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return Reserved;
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}
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const TargetRegisterClass*
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SystemZRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const {
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switch(Idx) {
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// Exact sub-classes don't exist for the other sub-register indexes.
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default: return 0;
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case SystemZ::subreg_32bit:
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if (B == SystemZ::ADDR32RegisterClass)
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return A->getSize() == 8 ? SystemZ::ADDR64RegisterClass : 0;
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return A;
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}
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}
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void SystemZRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MBB.erase(I);
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}
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void
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SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unxpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getIndex();
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unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
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// This must be part of a rri or ri operand memory reference. Replace the
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// FrameIndex with base register with BasePtr. Add an offset to the
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// displacement field.
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MI.getOperand(i).ChangeToRegister(BasePtr, false);
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// Offset is a either 12-bit unsigned or 20-bit signed integer.
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// FIXME: handle "too long" displacements.
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int Offset =
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TFI->getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
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// Check whether displacement is too long to fit into 12 bit zext field.
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MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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}
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unsigned
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SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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assert(0 && "What is the frame register");
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return 0;
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}
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unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
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assert(0 && "What is the exception register");
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return 0;
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}
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unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
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assert(0 && "What is the exception handler register");
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return 0;
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}
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