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04bcc11905
derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227113 91177308-0d34-0410-b5e6-96231b3b80d8
537 lines
19 KiB
C++
537 lines
19 KiB
C++
//===---------------------------- StackMaps.cpp ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <iterator>
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using namespace llvm;
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#define DEBUG_TYPE "stackmaps"
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static cl::opt<int> StackMapVersion("stackmap-version", cl::init(1),
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cl::desc("Specify the stackmap encoding version (default = 1)"));
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const char *StackMaps::WSMP = "Stack Maps: ";
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PatchPointOpers::PatchPointOpers(const MachineInstr *MI)
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: MI(MI),
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HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
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!MI->getOperand(0).isImplicit()),
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IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg)
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{
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#ifndef NDEBUG
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unsigned CheckStartIdx = 0, e = MI->getNumOperands();
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while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
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MI->getOperand(CheckStartIdx).isDef() &&
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!MI->getOperand(CheckStartIdx).isImplicit())
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++CheckStartIdx;
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assert(getMetaIdx() == CheckStartIdx &&
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"Unexpected additional definition in Patchpoint intrinsic.");
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#endif
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}
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unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
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if (!StartIdx)
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StartIdx = getVarIdx();
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// Find the next scratch register (implicit def and early clobber)
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unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
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while (ScratchIdx < e &&
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!(MI->getOperand(ScratchIdx).isReg() &&
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MI->getOperand(ScratchIdx).isDef() &&
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MI->getOperand(ScratchIdx).isImplicit() &&
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MI->getOperand(ScratchIdx).isEarlyClobber()))
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++ScratchIdx;
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assert(ScratchIdx != e && "No scratch register available");
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return ScratchIdx;
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}
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StackMaps::StackMaps(AsmPrinter &AP) : AP(AP) {
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if (StackMapVersion != 1)
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llvm_unreachable("Unsupported stackmap version!");
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}
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MachineInstr::const_mop_iterator
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StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE,
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LocationVec &Locs, LiveOutVec &LiveOuts) const {
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if (MOI->isImm()) {
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switch (MOI->getImm()) {
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default: llvm_unreachable("Unrecognized operand type.");
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case StackMaps::DirectMemRefOp: {
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unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits();
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assert((Size % 8) == 0 && "Need pointer size in bytes.");
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Size /= 8;
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unsigned Reg = (++MOI)->getReg();
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int64_t Imm = (++MOI)->getImm();
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Locs.push_back(Location(StackMaps::Location::Direct, Size, Reg, Imm));
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break;
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}
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case StackMaps::IndirectMemRefOp: {
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int64_t Size = (++MOI)->getImm();
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assert(Size > 0 && "Need a valid size for indirect memory locations.");
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unsigned Reg = (++MOI)->getReg();
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int64_t Imm = (++MOI)->getImm();
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Locs.push_back(Location(StackMaps::Location::Indirect, Size, Reg, Imm));
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break;
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}
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case StackMaps::ConstantOp: {
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++MOI;
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assert(MOI->isImm() && "Expected constant operand.");
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int64_t Imm = MOI->getImm();
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Locs.push_back(Location(Location::Constant, sizeof(int64_t), 0, Imm));
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break;
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}
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}
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return ++MOI;
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}
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// The physical register number will ultimately be encoded as a DWARF regno.
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// The stack map also records the size of a spill slot that can hold the
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// register content. (The runtime can track the actual size of the data type
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// if it needs to.)
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if (MOI->isReg()) {
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// Skip implicit registers (this includes our scratch registers)
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if (MOI->isImplicit())
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return ++MOI;
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assert(TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) &&
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"Virtreg operands should have been rewritten before now.");
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const TargetRegisterClass *RC =
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AP.TM.getSubtargetImpl()->getRegisterInfo()->getMinimalPhysRegClass(
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MOI->getReg());
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assert(!MOI->getSubReg() && "Physical subreg still around.");
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Locs.push_back(
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Location(Location::Register, RC->getSize(), MOI->getReg(), 0));
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return ++MOI;
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}
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if (MOI->isRegLiveOut())
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LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
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return ++MOI;
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}
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/// Go up the super-register chain until we hit a valid dwarf register number.
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static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
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int RegNo = TRI->getDwarfRegNum(Reg, false);
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for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNo < 0; ++SR)
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RegNo = TRI->getDwarfRegNum(*SR, false);
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assert(RegNo >= 0 && "Invalid Dwarf register number.");
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return (unsigned) RegNo;
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}
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/// Create a live-out register record for the given register Reg.
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StackMaps::LiveOutReg
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StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
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unsigned RegNo = getDwarfRegNum(Reg, TRI);
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unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
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return LiveOutReg(Reg, RegNo, Size);
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}
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/// Parse the register live-out mask and return a vector of live-out registers
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/// that need to be recorded in the stackmap.
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StackMaps::LiveOutVec
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StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
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assert(Mask && "No register mask specified");
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const TargetRegisterInfo *TRI = AP.TM.getSubtargetImpl()->getRegisterInfo();
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LiveOutVec LiveOuts;
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// Create a LiveOutReg for each bit that is set in the register mask.
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for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
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if ((Mask[Reg / 32] >> Reg % 32) & 1)
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LiveOuts.push_back(createLiveOutReg(Reg, TRI));
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// We don't need to keep track of a register if its super-register is already
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// in the list. Merge entries that refer to the same dwarf register and use
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// the maximum size that needs to be spilled.
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std::sort(LiveOuts.begin(), LiveOuts.end());
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for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end();
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I != E; ++I) {
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for (LiveOutVec::iterator II = std::next(I); II != E; ++II) {
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if (I->RegNo != II->RegNo) {
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// Skip all the now invalid entries.
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I = --II;
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break;
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}
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I->Size = std::max(I->Size, II->Size);
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if (TRI->isSuperRegister(I->Reg, II->Reg))
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I->Reg = II->Reg;
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II->MarkInvalid();
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}
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}
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LiveOuts.erase(std::remove_if(LiveOuts.begin(), LiveOuts.end(),
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LiveOutReg::IsInvalid), LiveOuts.end());
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return LiveOuts;
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}
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void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
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MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE,
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bool recordResult) {
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MCContext &OutContext = AP.OutStreamer.getContext();
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MCSymbol *MILabel = OutContext.CreateTempSymbol();
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AP.OutStreamer.EmitLabel(MILabel);
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LocationVec Locations;
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LiveOutVec LiveOuts;
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if (recordResult) {
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assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
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parseOperand(MI.operands_begin(), std::next(MI.operands_begin()),
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Locations, LiveOuts);
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}
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// Parse operands.
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while (MOI != MOE) {
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MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
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}
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// Move large constants into the constant pool.
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for (LocationVec::iterator I = Locations.begin(), E = Locations.end();
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I != E; ++I) {
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// Constants are encoded as sign-extended integers.
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// -1 is directly encoded as .long 0xFFFFFFFF with no constant pool.
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if (I->LocType == Location::Constant && !isInt<32>(I->Offset)) {
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I->LocType = Location::ConstantIndex;
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// ConstPool is intentionally a MapVector of 'uint64_t's (as
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// opposed to 'int64_t's). We should never be in a situation
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// where we have to insert either the tombstone or the empty
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// keys into a map, and for a DenseMap<uint64_t, T> these are
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// (uint64_t)0 and (uint64_t)-1. They can be and are
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// represented using 32 bit integers.
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assert((uint64_t)I->Offset != DenseMapInfo<uint64_t>::getEmptyKey() &&
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(uint64_t)I->Offset != DenseMapInfo<uint64_t>::getTombstoneKey() &&
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"empty and tombstone keys should fit in 32 bits!");
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auto Result = ConstPool.insert(std::make_pair(I->Offset, I->Offset));
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I->Offset = Result.first - ConstPool.begin();
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}
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}
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// Create an expression to calculate the offset of the callsite from function
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// entry.
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const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
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MCSymbolRefExpr::Create(MILabel, OutContext),
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MCSymbolRefExpr::Create(AP.CurrentFnSymForSize, OutContext),
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OutContext);
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CSInfos.emplace_back(CSOffsetExpr, ID, std::move(Locations),
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std::move(LiveOuts));
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// Record the stack size of the current function.
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const MachineFrameInfo *MFI = AP.MF->getFrameInfo();
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const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
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const bool DynamicFrameSize = MFI->hasVarSizedObjects() ||
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RegInfo->needsStackRealignment(*(AP.MF));
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FnStackSize[AP.CurrentFnSym] =
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DynamicFrameSize ? UINT64_MAX : MFI->getStackSize();
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}
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void StackMaps::recordStackMap(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
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int64_t ID = MI.getOperand(0).getImm();
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recordStackMapOpers(MI, ID, std::next(MI.operands_begin(), 2),
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MI.operands_end());
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}
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void StackMaps::recordPatchPoint(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
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PatchPointOpers opers(&MI);
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int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
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MachineInstr::const_mop_iterator MOI =
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std::next(MI.operands_begin(), opers.getStackMapStartIdx());
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recordStackMapOpers(MI, ID, MOI, MI.operands_end(),
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opers.isAnyReg() && opers.hasDef());
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#ifndef NDEBUG
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// verify anyregcc
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LocationVec &Locations = CSInfos.back().Locations;
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if (opers.isAnyReg()) {
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unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm();
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for (unsigned i = 0, e = (opers.hasDef() ? NArgs+1 : NArgs); i != e; ++i)
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assert(Locations[i].LocType == Location::Register &&
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"anyreg arg must be in reg.");
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}
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#endif
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}
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void StackMaps::recordStatepoint(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::STATEPOINT &&
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"expected statepoint");
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StatepointOpers opers(&MI);
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// Record all the deopt and gc operands (they're contiguous and run from the
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// initial index to the end of the operand list)
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const unsigned StartIdx = opers.getVarIdx();
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recordStackMapOpers(MI, 0xABCDEF00,
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MI.operands_begin() + StartIdx, MI.operands_end(),
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false);
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}
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/// Emit the stackmap header.
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///
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/// Header {
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/// uint8 : Stack Map Version (currently 1)
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/// uint8 : Reserved (expected to be 0)
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/// uint16 : Reserved (expected to be 0)
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/// }
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/// uint32 : NumFunctions
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/// uint32 : NumConstants
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/// uint32 : NumRecords
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void StackMaps::emitStackmapHeader(MCStreamer &OS) {
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// Header.
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OS.EmitIntValue(StackMapVersion, 1); // Version.
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OS.EmitIntValue(0, 1); // Reserved.
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OS.EmitIntValue(0, 2); // Reserved.
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// Num functions.
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DEBUG(dbgs() << WSMP << "#functions = " << FnStackSize.size() << '\n');
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OS.EmitIntValue(FnStackSize.size(), 4);
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// Num constants.
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DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.size() << '\n');
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OS.EmitIntValue(ConstPool.size(), 4);
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// Num callsites.
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DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n');
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OS.EmitIntValue(CSInfos.size(), 4);
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}
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/// Emit the function frame record for each function.
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///
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/// StkSizeRecord[NumFunctions] {
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/// uint64 : Function Address
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/// uint64 : Stack Size
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/// }
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void StackMaps::emitFunctionFrameRecords(MCStreamer &OS) {
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// Function Frame records.
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DEBUG(dbgs() << WSMP << "functions:\n");
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for (auto const &FR : FnStackSize) {
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DEBUG(dbgs() << WSMP << "function addr: " << FR.first
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<< " frame size: " << FR.second);
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OS.EmitSymbolValue(FR.first, 8);
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OS.EmitIntValue(FR.second, 8);
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}
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}
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/// Emit the constant pool.
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///
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/// int64 : Constants[NumConstants]
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void StackMaps::emitConstantPoolEntries(MCStreamer &OS) {
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// Constant pool entries.
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DEBUG(dbgs() << WSMP << "constants:\n");
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for (auto ConstEntry : ConstPool) {
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DEBUG(dbgs() << WSMP << ConstEntry.second << '\n');
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OS.EmitIntValue(ConstEntry.second, 8);
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}
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}
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/// Emit the callsite info for each callsite.
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///
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/// StkMapRecord[NumRecords] {
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/// uint64 : PatchPoint ID
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/// uint32 : Instruction Offset
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/// uint16 : Reserved (record flags)
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/// uint16 : NumLocations
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/// Location[NumLocations] {
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/// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
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/// uint8 : Size in Bytes
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/// uint16 : Dwarf RegNum
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/// int32 : Offset
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/// }
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/// uint16 : Padding
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/// uint16 : NumLiveOuts
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/// LiveOuts[NumLiveOuts] {
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/// uint16 : Dwarf RegNum
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/// uint8 : Reserved
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/// uint8 : Size in Bytes
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/// }
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/// uint32 : Padding (only if required to align to 8 byte)
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/// }
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///
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/// Location Encoding, Type, Value:
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/// 0x1, Register, Reg (value in register)
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/// 0x2, Direct, Reg + Offset (frame index)
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/// 0x3, Indirect, [Reg + Offset] (spilled value)
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/// 0x4, Constant, Offset (small constant)
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/// 0x5, ConstIndex, Constants[Offset] (large constant)
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void StackMaps::emitCallsiteEntries(MCStreamer &OS,
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const TargetRegisterInfo *TRI) {
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// Callsite entries.
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DEBUG(dbgs() << WSMP << "callsites:\n");
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for (const auto &CSI : CSInfos) {
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const LocationVec &CSLocs = CSI.Locations;
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const LiveOutVec &LiveOuts = CSI.LiveOuts;
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DEBUG(dbgs() << WSMP << "callsite " << CSI.ID << "\n");
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// Verify stack map entry. It's better to communicate a problem to the
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// runtime than crash in case of in-process compilation. Currently, we do
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// simple overflow checks, but we may eventually communicate other
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// compilation errors this way.
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if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
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OS.EmitIntValue(UINT64_MAX, 8); // Invalid ID.
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OS.EmitValue(CSI.CSOffsetExpr, 4);
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OS.EmitIntValue(0, 2); // Reserved.
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OS.EmitIntValue(0, 2); // 0 locations.
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OS.EmitIntValue(0, 2); // padding.
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OS.EmitIntValue(0, 2); // 0 live-out registers.
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OS.EmitIntValue(0, 4); // padding.
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continue;
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}
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OS.EmitIntValue(CSI.ID, 8);
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OS.EmitValue(CSI.CSOffsetExpr, 4);
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// Reserved for flags.
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OS.EmitIntValue(0, 2);
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DEBUG(dbgs() << WSMP << " has " << CSLocs.size() << " locations\n");
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OS.EmitIntValue(CSLocs.size(), 2);
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unsigned OperIdx = 0;
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for (const auto &Loc : CSLocs) {
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unsigned RegNo = 0;
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int Offset = Loc.Offset;
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if(Loc.Reg) {
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RegNo = getDwarfRegNum(Loc.Reg, TRI);
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// If this is a register location, put the subregister byte offset in
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// the location offset.
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if (Loc.LocType == Location::Register) {
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assert(!Loc.Offset && "Register location should have zero offset");
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unsigned LLVMRegNo = TRI->getLLVMRegNum(RegNo, false);
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unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNo, Loc.Reg);
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if (SubRegIdx)
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Offset = TRI->getSubRegIdxOffset(SubRegIdx);
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}
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}
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else {
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assert(Loc.LocType != Location::Register &&
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"Missing location register");
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}
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DEBUG(dbgs() << WSMP << " Loc " << OperIdx << ": ";
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switch (Loc.LocType) {
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|
case Location::Unprocessed:
|
|
dbgs() << "<Unprocessed operand>";
|
|
break;
|
|
case Location::Register:
|
|
dbgs() << "Register " << TRI->getName(Loc.Reg);
|
|
break;
|
|
case Location::Direct:
|
|
dbgs() << "Direct " << TRI->getName(Loc.Reg);
|
|
if (Loc.Offset)
|
|
dbgs() << " + " << Loc.Offset;
|
|
break;
|
|
case Location::Indirect:
|
|
dbgs() << "Indirect " << TRI->getName(Loc.Reg)
|
|
<< " + " << Loc.Offset;
|
|
break;
|
|
case Location::Constant:
|
|
dbgs() << "Constant " << Loc.Offset;
|
|
break;
|
|
case Location::ConstantIndex:
|
|
dbgs() << "Constant Index " << Loc.Offset;
|
|
break;
|
|
}
|
|
dbgs() << " [encoding: .byte " << Loc.LocType
|
|
<< ", .byte " << Loc.Size
|
|
<< ", .short " << RegNo
|
|
<< ", .int " << Offset << "]\n";
|
|
);
|
|
|
|
OS.EmitIntValue(Loc.LocType, 1);
|
|
OS.EmitIntValue(Loc.Size, 1);
|
|
OS.EmitIntValue(RegNo, 2);
|
|
OS.EmitIntValue(Offset, 4);
|
|
OperIdx++;
|
|
}
|
|
|
|
DEBUG(dbgs() << WSMP << " has " << LiveOuts.size()
|
|
<< " live-out registers\n");
|
|
|
|
// Num live-out registers and padding to align to 4 byte.
|
|
OS.EmitIntValue(0, 2);
|
|
OS.EmitIntValue(LiveOuts.size(), 2);
|
|
|
|
OperIdx = 0;
|
|
for (const auto &LO : LiveOuts) {
|
|
DEBUG(dbgs() << WSMP << " LO " << OperIdx << ": "
|
|
<< TRI->getName(LO.Reg)
|
|
<< " [encoding: .short " << LO.RegNo
|
|
<< ", .byte 0, .byte " << LO.Size << "]\n");
|
|
OS.EmitIntValue(LO.RegNo, 2);
|
|
OS.EmitIntValue(0, 1);
|
|
OS.EmitIntValue(LO.Size, 1);
|
|
}
|
|
// Emit alignment to 8 byte.
|
|
OS.EmitValueToAlignment(8);
|
|
}
|
|
}
|
|
|
|
/// Serialize the stackmap data.
|
|
void StackMaps::serializeToStackMapSection() {
|
|
(void) WSMP;
|
|
// Bail out if there's no stack map data.
|
|
assert((!CSInfos.empty() || (CSInfos.empty() && ConstPool.empty())) &&
|
|
"Expected empty constant pool too!");
|
|
assert((!CSInfos.empty() || (CSInfos.empty() && FnStackSize.empty())) &&
|
|
"Expected empty function record too!");
|
|
if (CSInfos.empty())
|
|
return;
|
|
|
|
MCContext &OutContext = AP.OutStreamer.getContext();
|
|
MCStreamer &OS = AP.OutStreamer;
|
|
const TargetRegisterInfo *TRI = AP.TM.getSubtargetImpl()->getRegisterInfo();
|
|
|
|
// Create the section.
|
|
const MCSection *StackMapSection =
|
|
OutContext.getObjectFileInfo()->getStackMapSection();
|
|
OS.SwitchSection(StackMapSection);
|
|
|
|
// Emit a dummy symbol to force section inclusion.
|
|
OS.EmitLabel(OutContext.GetOrCreateSymbol(Twine("__LLVM_StackMaps")));
|
|
|
|
// Serialize data.
|
|
DEBUG(dbgs() << "********** Stack Map Output **********\n");
|
|
emitStackmapHeader(OS);
|
|
emitFunctionFrameRecords(OS);
|
|
emitConstantPoolEntries(OS);
|
|
emitCallsiteEntries(OS, TRI);
|
|
OS.AddBlankLine();
|
|
|
|
// Clean up.
|
|
CSInfos.clear();
|
|
ConstPool.clear();
|
|
}
|