mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
3f7b7f8ce0
Also, some minor cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
877 lines
30 KiB
C++
877 lines
30 KiB
C++
//===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits code for use by the "fast" instruction
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// selection algorithm. See the comments at the top of
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// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
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//
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// This file scans through the target's tablegen instruction-info files
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// and extracts instructions with obvious-looking patterns, and it emits
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// code to look up these instructions by type and operator.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenDAGPatterns.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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/// InstructionMemo - This class holds additional information about an
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/// instruction needed to emit code for it.
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///
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namespace {
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struct InstructionMemo {
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std::string Name;
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const CodeGenRegisterClass *RC;
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std::string SubRegNo;
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std::vector<std::string>* PhysRegs;
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};
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} // End anonymous namespace
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/// ImmPredicateSet - This uniques predicates (represented as a string) and
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/// gives them unique (small) integer ID's that start at 0.
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namespace {
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class ImmPredicateSet {
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DenseMap<TreePattern *, unsigned> ImmIDs;
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std::vector<TreePredicateFn> PredsByName;
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public:
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unsigned getIDFor(TreePredicateFn Pred) {
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unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
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if (Entry == 0) {
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PredsByName.push_back(Pred);
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Entry = PredsByName.size();
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}
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return Entry-1;
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}
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const TreePredicateFn &getPredicate(unsigned i) {
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assert(i < PredsByName.size());
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return PredsByName[i];
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}
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typedef std::vector<TreePredicateFn>::const_iterator iterator;
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iterator begin() const { return PredsByName.begin(); }
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iterator end() const { return PredsByName.end(); }
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};
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} // End anonymous namespace
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/// OperandsSignature - This class holds a description of a list of operand
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/// types. It has utility methods for emitting text based on the operands.
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///
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namespace {
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struct OperandsSignature {
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class OpKind {
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enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
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char Repr;
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public:
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OpKind() : Repr(OK_Invalid) {}
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bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
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bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
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static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
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static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
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static OpKind getImm(unsigned V) {
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assert((unsigned)OK_Imm+V < 128 &&
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"Too many integer predicates for the 'Repr' char");
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OpKind K; K.Repr = OK_Imm+V; return K;
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}
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bool isReg() const { return Repr == OK_Reg; }
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bool isFP() const { return Repr == OK_FP; }
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bool isImm() const { return Repr >= OK_Imm; }
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unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; }
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void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
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bool StripImmCodes) const {
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if (isReg())
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OS << 'r';
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else if (isFP())
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OS << 'f';
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else {
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OS << 'i';
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if (!StripImmCodes)
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if (unsigned Code = getImmCode())
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OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
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}
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}
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};
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SmallVector<OpKind, 3> Operands;
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bool operator<(const OperandsSignature &O) const {
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return Operands < O.Operands;
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}
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bool operator==(const OperandsSignature &O) const {
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return Operands == O.Operands;
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}
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bool empty() const { return Operands.empty(); }
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bool hasAnyImmediateCodes() const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i)
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if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
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return true;
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return false;
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}
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/// getWithoutImmCodes - Return a copy of this with any immediate codes forced
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/// to zero.
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OperandsSignature getWithoutImmCodes() const {
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OperandsSignature Result;
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for (unsigned i = 0, e = Operands.size(); i != e; ++i)
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if (!Operands[i].isImm())
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Result.Operands.push_back(Operands[i]);
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else
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Result.Operands.push_back(OpKind::getImm(0));
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return Result;
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}
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void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
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bool EmittedAnything = false;
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (!Operands[i].isImm()) continue;
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unsigned Code = Operands[i].getImmCode();
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if (Code == 0) continue;
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if (EmittedAnything)
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OS << " &&\n ";
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TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
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// Emit the type check.
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OS << "VT == "
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<< getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0))
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<< " && ";
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OS << PredFn.getFnName() << "(imm" << i <<')';
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EmittedAnything = true;
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}
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}
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/// initialize - Examine the given pattern and initialize the contents
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/// of the Operands array accordingly. Return true if all the operands
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/// are supported, false otherwise.
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///
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bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
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MVT::SimpleValueType VT,
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ImmPredicateSet &ImmediatePredicates) {
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if (InstPatNode->isLeaf())
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return false;
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if (InstPatNode->getOperator()->getName() == "imm") {
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Operands.push_back(OpKind::getImm(0));
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return true;
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}
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if (InstPatNode->getOperator()->getName() == "fpimm") {
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Operands.push_back(OpKind::getFP());
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return true;
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}
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const CodeGenRegisterClass *DstRC = 0;
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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// Handle imm operands specially.
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if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
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unsigned PredNo = 0;
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if (!Op->getPredicateFns().empty()) {
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TreePredicateFn PredFn = Op->getPredicateFns()[0];
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// If there is more than one predicate weighing in on this operand
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// then we don't handle it. This doesn't typically happen for
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// immediates anyway.
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if (Op->getPredicateFns().size() > 1 ||
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!PredFn.isImmediatePattern())
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return false;
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// Ignore any instruction with 'FastIselShouldIgnore', these are
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// not needed and just bloat the fast instruction selector. For
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// example, X86 doesn't need to generate code to match ADD16ri8 since
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// ADD16ri will do just fine.
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Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
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if (Rec->getValueAsBit("FastIselShouldIgnore"))
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return false;
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PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
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}
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// Handle unmatched immediate sizes here.
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//if (Op->getType(0) != VT)
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// return false;
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Operands.push_back(OpKind::getImm(PredNo));
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continue;
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}
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// For now, filter out any operand with a predicate.
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// For now, filter out any operand with multiple values.
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if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
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return false;
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if (!Op->isLeaf()) {
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if (Op->getOperator()->getName() == "fpimm") {
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Operands.push_back(OpKind::getFP());
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continue;
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}
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// For now, ignore other non-leaf nodes.
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return false;
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}
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assert(Op->hasTypeSet(0) && "Type infererence not done?");
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// For now, all the operands must have the same type (if they aren't
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// immediates). Note that this causes us to reject variable sized shifts
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// on X86.
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if (Op->getType(0) != VT)
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return false;
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DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue());
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if (!OpDI)
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return false;
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Record *OpLeafRec = OpDI->getDef();
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// For now, the only other thing we accept is register operands.
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const CodeGenRegisterClass *RC = 0;
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if (OpLeafRec->isSubClassOf("RegisterOperand"))
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OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
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if (OpLeafRec->isSubClassOf("RegisterClass"))
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RC = &Target.getRegisterClass(OpLeafRec);
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else if (OpLeafRec->isSubClassOf("Register"))
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RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
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else
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return false;
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// For now, this needs to be a register class of some sort.
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if (!RC)
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return false;
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// For now, all the operands must have the same register class or be
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// a strict subclass of the destination.
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if (DstRC) {
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if (DstRC != RC && !DstRC->hasSubClass(RC))
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return false;
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} else
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DstRC = RC;
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Operands.push_back(OpKind::getReg());
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}
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return true;
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}
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void PrintParameters(raw_ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i].isReg()) {
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OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
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} else if (Operands[i].isImm()) {
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OS << "uint64_t imm" << i;
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} else if (Operands[i].isFP()) {
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OS << "const ConstantFP *f" << i;
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} else {
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llvm_unreachable("Unknown operand kind!");
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintArguments(raw_ostream &OS,
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const std::vector<std::string> &PR) const {
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assert(PR.size() == Operands.size());
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bool PrintedArg = false;
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (PR[i] != "")
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// Implicit physical register operand.
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continue;
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if (PrintedArg)
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OS << ", ";
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if (Operands[i].isReg()) {
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OS << "Op" << i << ", Op" << i << "IsKill";
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PrintedArg = true;
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} else if (Operands[i].isImm()) {
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OS << "imm" << i;
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PrintedArg = true;
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} else if (Operands[i].isFP()) {
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OS << "f" << i;
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PrintedArg = true;
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} else {
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llvm_unreachable("Unknown operand kind!");
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}
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}
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}
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void PrintArguments(raw_ostream &OS) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i].isReg()) {
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OS << "Op" << i << ", Op" << i << "IsKill";
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} else if (Operands[i].isImm()) {
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OS << "imm" << i;
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} else if (Operands[i].isFP()) {
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OS << "f" << i;
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} else {
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llvm_unreachable("Unknown operand kind!");
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}
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if (i + 1 != e)
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OS << ", ";
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}
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}
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void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
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ImmPredicateSet &ImmPredicates,
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bool StripImmCodes = false) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (PR[i] != "")
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// Implicit physical register operand. e.g. Instruction::Mul expect to
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// select to a binary op. On x86, mul may take a single operand with
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// the other operand being implicit. We must emit something that looks
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// like a binary instruction except for the very inner FastEmitInst_*
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// call.
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continue;
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Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
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}
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}
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void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
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bool StripImmCodes = false) const {
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for (unsigned i = 0, e = Operands.size(); i != e; ++i)
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Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
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}
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};
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} // End anonymous namespace
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namespace {
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class FastISelMap {
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typedef std::map<std::string, InstructionMemo> PredMap;
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typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
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typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
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typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
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typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
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OperandsOpcodeTypeRetPredMap;
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OperandsOpcodeTypeRetPredMap SimplePatterns;
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std::map<OperandsSignature, std::vector<OperandsSignature> >
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SignaturesWithConstantForms;
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std::string InstNS;
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ImmPredicateSet ImmediatePredicates;
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public:
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explicit FastISelMap(std::string InstNS);
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void collectPatterns(CodeGenDAGPatterns &CGP);
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void printImmediatePredicates(raw_ostream &OS);
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void printFunctionDefinitions(raw_ostream &OS);
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};
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} // End anonymous namespace
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static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
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return CGP.getSDNodeInfo(Op).getEnumName();
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}
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static std::string getLegalCName(std::string OpName) {
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std::string::size_type pos = OpName.find("::");
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if (pos != std::string::npos)
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OpName.replace(pos, 2, "_");
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return OpName;
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}
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FastISelMap::FastISelMap(std::string instns)
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: InstNS(instns) {
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}
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static std::string PhyRegForNode(TreePatternNode *Op,
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const CodeGenTarget &Target) {
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std::string PhysReg;
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if (!Op->isLeaf())
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return PhysReg;
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Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef();
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if (!OpLeafRec->isSubClassOf("Register"))
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return PhysReg;
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PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
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->getValue();
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PhysReg += "::";
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PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
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return PhysReg;
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}
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void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
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const CodeGenTarget &Target = CGP.getTargetInfo();
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// Determine the target's namespace name.
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InstNS = Target.getInstNamespace() + "::";
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assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
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// Scan through all the patterns and record the simple ones.
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for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
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E = CGP.ptm_end(); I != E; ++I) {
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const PatternToMatch &Pattern = *I;
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// For now, just look at Instructions, so that we don't have to worry
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// about emitting multiple instructions for a pattern.
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TreePatternNode *Dst = Pattern.getDstPattern();
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if (Dst->isLeaf()) continue;
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Record *Op = Dst->getOperator();
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if (!Op->isSubClassOf("Instruction"))
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continue;
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CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
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if (II.Operands.empty())
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continue;
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// For now, ignore multi-instruction patterns.
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bool MultiInsts = false;
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for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
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TreePatternNode *ChildOp = Dst->getChild(i);
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if (ChildOp->isLeaf())
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continue;
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if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
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MultiInsts = true;
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break;
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}
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}
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if (MultiInsts)
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continue;
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// For now, ignore instructions where the first operand is not an
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// output register.
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const CodeGenRegisterClass *DstRC = 0;
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std::string SubRegNo;
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if (Op->getName() != "EXTRACT_SUBREG") {
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Record *Op0Rec = II.Operands[0].Rec;
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if (Op0Rec->isSubClassOf("RegisterOperand"))
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Op0Rec = Op0Rec->getValueAsDef("RegClass");
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if (!Op0Rec->isSubClassOf("RegisterClass"))
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continue;
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DstRC = &Target.getRegisterClass(Op0Rec);
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if (!DstRC)
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continue;
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} else {
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// If this isn't a leaf, then continue since the register classes are
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// a bit too complicated for now.
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if (!Dst->getChild(1)->isLeaf()) continue;
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DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
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if (SR)
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SubRegNo = getQualifiedName(SR->getDef());
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else
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SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
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}
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// Inspect the pattern.
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TreePatternNode *InstPatNode = Pattern.getSrcPattern();
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if (!InstPatNode) continue;
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if (InstPatNode->isLeaf()) continue;
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// Ignore multiple result nodes for now.
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if (InstPatNode->getNumTypes() > 1) continue;
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Record *InstPatOp = InstPatNode->getOperator();
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std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
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MVT::SimpleValueType RetVT = MVT::isVoid;
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if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0);
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MVT::SimpleValueType VT = RetVT;
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if (InstPatNode->getNumChildren()) {
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assert(InstPatNode->getChild(0)->getNumTypes() == 1);
|
|
VT = InstPatNode->getChild(0)->getType(0);
|
|
}
|
|
|
|
// For now, filter out any instructions with predicates.
|
|
if (!InstPatNode->getPredicateFns().empty())
|
|
continue;
|
|
|
|
// Check all the operands.
|
|
OperandsSignature Operands;
|
|
if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
|
|
continue;
|
|
|
|
std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
|
|
if (InstPatNode->getOperator()->getName() == "imm" ||
|
|
InstPatNode->getOperator()->getName() == "fpimm")
|
|
PhysRegInputs->push_back("");
|
|
else {
|
|
// Compute the PhysRegs used by the given pattern, and check that
|
|
// the mapping from the src to dst patterns is simple.
|
|
bool FoundNonSimplePattern = false;
|
|
unsigned DstIndex = 0;
|
|
for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
|
|
std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
|
|
if (PhysReg.empty()) {
|
|
if (DstIndex >= Dst->getNumChildren() ||
|
|
Dst->getChild(DstIndex)->getName() !=
|
|
InstPatNode->getChild(i)->getName()) {
|
|
FoundNonSimplePattern = true;
|
|
break;
|
|
}
|
|
++DstIndex;
|
|
}
|
|
|
|
PhysRegInputs->push_back(PhysReg);
|
|
}
|
|
|
|
if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
|
|
FoundNonSimplePattern = true;
|
|
|
|
if (FoundNonSimplePattern)
|
|
continue;
|
|
}
|
|
|
|
// Get the predicate that guards this pattern.
|
|
std::string PredicateCheck = Pattern.getPredicateCheck();
|
|
|
|
// Ok, we found a pattern that we can handle. Remember it.
|
|
InstructionMemo Memo = {
|
|
Pattern.getDstPattern()->getOperator()->getName(),
|
|
DstRC,
|
|
SubRegNo,
|
|
PhysRegInputs
|
|
};
|
|
|
|
if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
|
|
throw TGError(Pattern.getSrcRecord()->getLoc(),
|
|
"Duplicate record in FastISel table!");
|
|
|
|
SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
|
|
|
|
// If any of the operands were immediates with predicates on them, strip
|
|
// them down to a signature that doesn't have predicates so that we can
|
|
// associate them with the stripped predicate version.
|
|
if (Operands.hasAnyImmediateCodes()) {
|
|
SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
|
|
.push_back(Operands);
|
|
}
|
|
}
|
|
}
|
|
|
|
void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
|
|
if (ImmediatePredicates.begin() == ImmediatePredicates.end())
|
|
return;
|
|
|
|
OS << "\n// FastEmit Immediate Predicate functions.\n";
|
|
for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
|
|
E = ImmediatePredicates.end(); I != E; ++I) {
|
|
OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
|
|
OS << I->getImmediatePredicateCode() << "\n}\n";
|
|
}
|
|
|
|
OS << "\n\n";
|
|
}
|
|
|
|
|
|
void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
|
|
// Now emit code for all the patterns that we collected.
|
|
for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
|
|
OE = SimplePatterns.end(); OI != OE; ++OI) {
|
|
const OperandsSignature &Operands = OI->first;
|
|
const OpcodeTypeRetPredMap &OTM = OI->second;
|
|
|
|
for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
|
|
I != E; ++I) {
|
|
const std::string &Opcode = I->first;
|
|
const TypeRetPredMap &TM = I->second;
|
|
|
|
OS << "// FastEmit functions for " << Opcode << ".\n";
|
|
OS << "\n";
|
|
|
|
// Emit one function for each opcode,type pair.
|
|
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
|
|
TI != TE; ++TI) {
|
|
MVT::SimpleValueType VT = TI->first;
|
|
const RetPredMap &RM = TI->second;
|
|
if (RM.size() != 1) {
|
|
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
|
|
RI != RE; ++RI) {
|
|
MVT::SimpleValueType RetVT = RI->first;
|
|
const PredMap &PM = RI->second;
|
|
bool HasPred = false;
|
|
|
|
OS << "unsigned FastEmit_"
|
|
<< getLegalCName(Opcode)
|
|
<< "_" << getLegalCName(getName(VT))
|
|
<< "_" << getLegalCName(getName(RetVT)) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\n";
|
|
|
|
// Emit code for each possible instruction. There may be
|
|
// multiple if there are subtarget concerns.
|
|
for (PredMap::const_iterator PI = PM.begin(), PE = PM.end();
|
|
PI != PE; ++PI) {
|
|
std::string PredicateCheck = PI->first;
|
|
const InstructionMemo &Memo = PI->second;
|
|
|
|
if (PredicateCheck.empty()) {
|
|
assert(!HasPred &&
|
|
"Multiple instructions match, at least one has "
|
|
"a predicate and at least one doesn't!");
|
|
} else {
|
|
OS << " if (" + PredicateCheck + ") {\n";
|
|
OS << " ";
|
|
HasPred = true;
|
|
}
|
|
|
|
for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
|
|
if ((*Memo.PhysRegs)[i] != "")
|
|
OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
|
|
<< "TII.get(TargetOpcode::COPY), "
|
|
<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
|
|
}
|
|
|
|
OS << " return FastEmitInst_";
|
|
if (Memo.SubRegNo.empty()) {
|
|
Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
|
|
ImmediatePredicates, true);
|
|
OS << "(" << InstNS << Memo.Name << ", ";
|
|
OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS, *Memo.PhysRegs);
|
|
OS << ");\n";
|
|
} else {
|
|
OS << "extractsubreg(" << getName(RetVT);
|
|
OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
|
|
}
|
|
|
|
if (HasPred)
|
|
OS << " }\n";
|
|
|
|
}
|
|
// Return 0 if none of the predicates were satisfied.
|
|
if (HasPred)
|
|
OS << " return 0;\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
|
|
// Emit one function for the type that demultiplexes on return type.
|
|
OS << "unsigned FastEmit_"
|
|
<< getLegalCName(Opcode) << "_"
|
|
<< getLegalCName(getName(VT)) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(MVT RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\nswitch (RetVT.SimpleTy) {\n";
|
|
for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
|
|
RI != RE; ++RI) {
|
|
MVT::SimpleValueType RetVT = RI->first;
|
|
OS << " case " << getName(RetVT) << ": return FastEmit_"
|
|
<< getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
|
|
<< "_" << getLegalCName(getName(RetVT)) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(";
|
|
Operands.PrintArguments(OS);
|
|
OS << ");\n";
|
|
}
|
|
OS << " default: return 0;\n}\n}\n\n";
|
|
|
|
} else {
|
|
// Non-variadic return type.
|
|
OS << "unsigned FastEmit_"
|
|
<< getLegalCName(Opcode) << "_"
|
|
<< getLegalCName(getName(VT)) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(MVT RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\n";
|
|
|
|
OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
|
|
<< ")\n return 0;\n";
|
|
|
|
const PredMap &PM = RM.begin()->second;
|
|
bool HasPred = false;
|
|
|
|
// Emit code for each possible instruction. There may be
|
|
// multiple if there are subtarget concerns.
|
|
for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE;
|
|
++PI) {
|
|
std::string PredicateCheck = PI->first;
|
|
const InstructionMemo &Memo = PI->second;
|
|
|
|
if (PredicateCheck.empty()) {
|
|
assert(!HasPred &&
|
|
"Multiple instructions match, at least one has "
|
|
"a predicate and at least one doesn't!");
|
|
} else {
|
|
OS << " if (" + PredicateCheck + ") {\n";
|
|
OS << " ";
|
|
HasPred = true;
|
|
}
|
|
|
|
for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
|
|
if ((*Memo.PhysRegs)[i] != "")
|
|
OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, "
|
|
<< "TII.get(TargetOpcode::COPY), "
|
|
<< (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
|
|
}
|
|
|
|
OS << " return FastEmitInst_";
|
|
|
|
if (Memo.SubRegNo.empty()) {
|
|
Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
|
|
ImmediatePredicates, true);
|
|
OS << "(" << InstNS << Memo.Name << ", ";
|
|
OS << "&" << InstNS << Memo.RC->getName() << "RegClass";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS, *Memo.PhysRegs);
|
|
OS << ");\n";
|
|
} else {
|
|
OS << "extractsubreg(RetVT, Op0, Op0IsKill, ";
|
|
OS << Memo.SubRegNo;
|
|
OS << ");\n";
|
|
}
|
|
|
|
if (HasPred)
|
|
OS << " }\n";
|
|
}
|
|
|
|
// Return 0 if none of the predicates were satisfied.
|
|
if (HasPred)
|
|
OS << " return 0;\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
}
|
|
|
|
// Emit one function for the opcode that demultiplexes based on the type.
|
|
OS << "unsigned FastEmit_"
|
|
<< getLegalCName(Opcode) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(MVT VT, MVT RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\n";
|
|
OS << " switch (VT.SimpleTy) {\n";
|
|
for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
|
|
TI != TE; ++TI) {
|
|
MVT::SimpleValueType VT = TI->first;
|
|
std::string TypeName = getName(VT);
|
|
OS << " case " << TypeName << ": return FastEmit_"
|
|
<< getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS);
|
|
OS << ");\n";
|
|
}
|
|
OS << " default: return 0;\n";
|
|
OS << " }\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
|
|
OS << "// Top-level FastEmit function.\n";
|
|
OS << "\n";
|
|
|
|
// Emit one function for the operand signature that demultiplexes based
|
|
// on opcode and type.
|
|
OS << "unsigned FastEmit_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(MVT VT, MVT RetVT, unsigned Opcode";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintParameters(OS);
|
|
OS << ") {\n";
|
|
|
|
// If there are any forms of this signature available that operand on
|
|
// constrained forms of the immediate (e.g. 32-bit sext immediate in a
|
|
// 64-bit operand), check them first.
|
|
|
|
std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
|
|
= SignaturesWithConstantForms.find(Operands);
|
|
if (MI != SignaturesWithConstantForms.end()) {
|
|
// Unique any duplicates out of the list.
|
|
std::sort(MI->second.begin(), MI->second.end());
|
|
MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
|
|
MI->second.end());
|
|
|
|
// Check each in order it was seen. It would be nice to have a good
|
|
// relative ordering between them, but we're not going for optimality
|
|
// here.
|
|
for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
|
|
OS << " if (";
|
|
MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
|
|
OS << ")\n if (unsigned Reg = FastEmit_";
|
|
MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(VT, RetVT, Opcode";
|
|
if (!MI->second[i].empty())
|
|
OS << ", ";
|
|
MI->second[i].PrintArguments(OS);
|
|
OS << "))\n return Reg;\n\n";
|
|
}
|
|
|
|
// Done with this, remove it.
|
|
SignaturesWithConstantForms.erase(MI);
|
|
}
|
|
|
|
OS << " switch (Opcode) {\n";
|
|
for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
|
|
I != E; ++I) {
|
|
const std::string &Opcode = I->first;
|
|
|
|
OS << " case " << Opcode << ": return FastEmit_"
|
|
<< getLegalCName(Opcode) << "_";
|
|
Operands.PrintManglingSuffix(OS, ImmediatePredicates);
|
|
OS << "(VT, RetVT";
|
|
if (!Operands.empty())
|
|
OS << ", ";
|
|
Operands.PrintArguments(OS);
|
|
OS << ");\n";
|
|
}
|
|
OS << " default: return 0;\n";
|
|
OS << " }\n";
|
|
OS << "}\n";
|
|
OS << "\n";
|
|
}
|
|
|
|
// TODO: SignaturesWithConstantForms should be empty here.
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
|
|
CodeGenDAGPatterns CGP(RK);
|
|
const CodeGenTarget &Target = CGP.getTargetInfo();
|
|
emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
|
|
Target.getName() + " target", OS);
|
|
|
|
// Determine the target's namespace name.
|
|
std::string InstNS = Target.getInstNamespace() + "::";
|
|
assert(InstNS.size() > 2 && "Can't determine target-specific namespace!");
|
|
|
|
FastISelMap F(InstNS);
|
|
F.collectPatterns(CGP);
|
|
F.printImmediatePredicates(OS);
|
|
F.printFunctionDefinitions(OS);
|
|
}
|
|
|
|
} // End llvm namespace
|