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7bbb9c7b4a
On PowerPC, a bitcast of <16 x i8> to i128 may run through a code path in ExpandRes_BITCAST that attempts to do an intermediate bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts of the resulting i128 by pairing up two of those i32 vector elements each. The code already recognizes that on a big-endian system, the first two vector elements form the Hi part, and the final two vector elements form the Lo part (vice-versa from the little-endian situation). However, we also need to take endianness into account when forming each of those separate pairs: on a big-endian system, vector element 0 is the *high* part of the pair making up the Hi part of the result, and vector element 1 is the low part of the pair. The code currently always uses vector element 0 as the low part and vector element 1 as the high part, as is appropriate for little-endian platforms only. This patch fixes this by swapping the vector elements as they are paired up as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165802 91177308-0d34-0410-b5e6-96231b3b80d8
21 lines
581 B
LLVM
21 lines
581 B
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i32 @test(<16 x i8> %v) nounwind {
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entry:
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%0 = bitcast <16 x i8> %v to i128
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%1 = lshr i128 %0, 96
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%2 = trunc i128 %1 to i32
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ret i32 %2
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}
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; Verify that bitcast handles big-endian platforms correctly
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; by checking we load the result from the correct offset
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; CHECK: addi [[REGISTER:[0-9]+]], 1, -16
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; CHECK: stvx 2, 0, [[REGISTER]]
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; CHECK: lwz 3, -16(1)
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; CHECK: blr
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