mirror of
https://github.com/c64scene-ar/llvm-6502.git
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5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
1.1 KiB
LLVM
29 lines
1.1 KiB
LLVM
; RUN: llc --march=x86 --mcpu=x86-64 --mattr=ssse3 < %s
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; RUN: llc --march=x86-64 --mcpu=x86-64 --mattr=ssse3 < %s
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;PR18045:
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;Issue of selection for 'v4i32 load'.
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;This instruction is not legal for X86 CPUs with sse < 'sse4.1'.
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;This node was generated by X86ISelLowering.cpp, EltsFromConsecutiveLoads
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;static function after legalize stage.
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@e = external global [4 x i32], align 4
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@f = external global [4 x i32], align 4
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; Function Attrs: nounwind
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define void @fn3(i32 %el) {
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entry:
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%0 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 0)
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%1 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 1)
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%2 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 2)
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%3 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* @e, i32 0, i32 3)
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%4 = insertelement <4 x i32> undef, i32 %0, i32 0
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%5 = insertelement <4 x i32> %4, i32 %1, i32 1
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%6 = insertelement <4 x i32> %5, i32 %2, i32 2
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%7 = insertelement <4 x i32> %6, i32 %3, i32 3
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%8 = add <4 x i32> %6, %7
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store <4 x i32> %8, <4 x i32>* bitcast ([4 x i32]* @f to <4 x i32>*)
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ret void
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}
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