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https://github.com/c64scene-ar/llvm-6502.git
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8f01b96d93
Targets which provide a rotate make it possible to replace a sequence of (XOR (SHL 1, x), -1) with (ROTL ~1, x). This saves an instruction on architectures like X86 and POWER(64). Differential Revision: http://reviews.llvm.org/D8350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232572 91177308-0d34-0410-b5e6-96231b3b80d8
196 lines
4.8 KiB
LLVM
196 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 | FileCheck %s -check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 | FileCheck %s -check-prefix=X64
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; Though it is undefined, we want xor undef,undef to produce zero.
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define <4 x i32> @test1() nounwind {
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%tmp = xor <4 x i32> undef, undef
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ret <4 x i32> %tmp
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; X32-LABEL: test1:
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; X32: xorps %xmm0, %xmm0
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; X32: ret
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}
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; Though it is undefined, we want xor undef,undef to produce zero.
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define i32 @test2() nounwind{
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%tmp = xor i32 undef, undef
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ret i32 %tmp
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; X32-LABEL: test2:
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; X32: xorl %eax, %eax
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; X32: ret
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}
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define i32 @test3(i32 %a, i32 %b) nounwind {
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entry:
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%tmp1not = xor i32 %b, -2
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%tmp3 = and i32 %tmp1not, %a
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%tmp4 = lshr i32 %tmp3, 1
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ret i32 %tmp4
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; X64-LABEL: test3:
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; X64: notl
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; X64: andl
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; X64: shrl
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; X64: ret
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; X32-LABEL: test3:
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; X32: movl 8(%esp), %eax
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; X32: notl %eax
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; X32: andl 4(%esp), %eax
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; X32: shrl %eax
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; X32: ret
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}
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define i32 @test4(i32 %a, i32 %b) nounwind {
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entry:
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br label %bb
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bb:
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%b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
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%a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
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%tmp3 = xor i32 %a_addr.0, %b_addr.0
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%tmp4not = xor i32 %tmp3, 2147483647
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%tmp6 = and i32 %tmp4not, %b_addr.0
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%tmp8 = shl i32 %tmp6, 1
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%tmp10 = icmp eq i32 %tmp8, 0
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br i1 %tmp10, label %bb12, label %bb
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bb12:
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ret i32 %tmp3
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; X64-LABEL: test4:
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; X64: notl [[REG:%[a-z]+]]
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; X64: andl {{.*}}[[REG]]
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; X32-LABEL: test4:
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; X32: notl [[REG:%[a-z]+]]
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; X32: andl {{.*}}[[REG]]
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}
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define i16 @test5(i16 %a, i16 %b) nounwind {
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entry:
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br label %bb
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bb:
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%b_addr.0 = phi i16 [ %b, %entry ], [ %tmp8, %bb ]
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%a_addr.0 = phi i16 [ %a, %entry ], [ %tmp3, %bb ]
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%tmp3 = xor i16 %a_addr.0, %b_addr.0
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%tmp4not = xor i16 %tmp3, 32767
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%tmp6 = and i16 %tmp4not, %b_addr.0
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%tmp8 = shl i16 %tmp6, 1
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%tmp10 = icmp eq i16 %tmp8, 0
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br i1 %tmp10, label %bb12, label %bb
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bb12:
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ret i16 %tmp3
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; X64-LABEL: test5:
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; X64: notl [[REG:%[a-z]+]]
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; X64: andl {{.*}}[[REG]]
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; X32-LABEL: test5:
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; X32: notl [[REG:%[a-z]+]]
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; X32: andl {{.*}}[[REG]]
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}
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define i8 @test6(i8 %a, i8 %b) nounwind {
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entry:
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br label %bb
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bb:
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%b_addr.0 = phi i8 [ %b, %entry ], [ %tmp8, %bb ]
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%a_addr.0 = phi i8 [ %a, %entry ], [ %tmp3, %bb ]
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%tmp3 = xor i8 %a_addr.0, %b_addr.0
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%tmp4not = xor i8 %tmp3, 127
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%tmp6 = and i8 %tmp4not, %b_addr.0
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%tmp8 = shl i8 %tmp6, 1
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%tmp10 = icmp eq i8 %tmp8, 0
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br i1 %tmp10, label %bb12, label %bb
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bb12:
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ret i8 %tmp3
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; X64-LABEL: test6:
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; X64: notb [[REG:%[a-z]+]]
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; X64: andb {{.*}}[[REG]]
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; X32-LABEL: test6:
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; X32: notb [[REG:%[a-z]+]]
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; X32: andb {{.*}}[[REG]]
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}
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define i32 @test7(i32 %a, i32 %b) nounwind {
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entry:
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br label %bb
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bb:
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%b_addr.0 = phi i32 [ %b, %entry ], [ %tmp8, %bb ]
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%a_addr.0 = phi i32 [ %a, %entry ], [ %tmp3, %bb ]
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%tmp3 = xor i32 %a_addr.0, %b_addr.0
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%tmp4not = xor i32 %tmp3, 2147483646
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%tmp6 = and i32 %tmp4not, %b_addr.0
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%tmp8 = shl i32 %tmp6, 1
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%tmp10 = icmp eq i32 %tmp8, 0
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br i1 %tmp10, label %bb12, label %bb
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bb12:
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ret i32 %tmp3
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; X64-LABEL: test7:
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; X64: xorl $2147483646, [[REG:%[a-z]+]]
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; X64: andl {{.*}}[[REG]]
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; X32-LABEL: test7:
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; X32: xorl $2147483646, [[REG:%[a-z]+]]
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; X32: andl {{.*}}[[REG]]
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}
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define i32 @test8(i32 %a) nounwind {
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; rdar://7553032
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entry:
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%t1 = sub i32 0, %a
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%t2 = add i32 %t1, -1
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ret i32 %t2
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; X64-LABEL: test8:
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; X64: notl {{%eax|%edi|%ecx}}
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; X32-LABEL: test8:
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; X32: notl %eax
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}
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define i32 @test9(i32 %a) nounwind {
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%1 = and i32 %a, 4096
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%2 = xor i32 %1, 4096
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ret i32 %2
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; X64-LABEL: test9:
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; X64: notl [[REG:%[a-z]+]]
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; X64: andl {{.*}}[[REG:%[a-z]+]]
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; X32-LABEL: test9:
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; X32: notl [[REG:%[a-z]+]]
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; X32: andl {{.*}}[[REG:%[a-z]+]]
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}
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; PR15948
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define <4 x i32> @test10(<4 x i32> %a) nounwind {
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%1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
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%2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
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ret <4 x i32> %2
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; X64-LABEL: test10:
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; X64: andnps
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; X32-LABEL: test10:
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; X32: andnps
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}
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define i32 @PR17487(i1 %tobool) {
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%tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1
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%tmp1 = zext <2 x i1> %tmp to <2 x i64>
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%tmp2 = xor <2 x i64> %tmp1, <i64 1, i64 1>
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%tmp3 = extractelement <2 x i64> %tmp2, i32 1
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%add = add nsw i64 0, %tmp3
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%cmp6 = icmp ne i64 %add, 1
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%conv7 = zext i1 %cmp6 to i32
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ret i32 %conv7
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; X64-LABEL: PR17487:
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; X64: andn
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; X32-LABEL: PR17487:
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; X32: andn
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}
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define i32 @test11(i32 %b) {
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%shl = shl i32 1, %b
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%neg = xor i32 %shl, -1
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ret i32 %neg
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; X64-LABEL: test11:
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; X64: movl $-2, %[[REG:.*]]
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; X64: roll %{{.*}}, %[[REG]]
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; X32-LABEL: test11:
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; X32: movl $-2, %[[REG:.*]]
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; X32: roll %{{.*}}, %[[REG]]
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}
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