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7e6565112b
This matches the internal behavior of NVIDIA tools like libnvvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213168 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
2.8 KiB
TableGen
70 lines
2.8 KiB
TableGen
//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class NVPTXReg<string n> : Register<n> {
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let Namespace = "NVPTX";
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}
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class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
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: RegisterClass <"NVPTX", regTypes, alignment, regList>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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// Special Registers used as stack pointer
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def VRFrame : NVPTXReg<"%SP">;
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def VRFrameLocal : NVPTXReg<"%SPL">;
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// Special Registers used as the stack
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def VRDepot : NVPTXReg<"%Depot">;
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// We use virtual registers, but define a few physical registers here to keep
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// SDAG and the MachineInstr layers happy.
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foreach i = 0-4 in {
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def P#i : NVPTXReg<"%p"#i>; // Predicate
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def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
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def R#i : NVPTXReg<"%r"#i>; // 32-bit
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def RL#i : NVPTXReg<"%rd"#i>; // 64-bit
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def F#i : NVPTXReg<"%f"#i>; // 32-bit float
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def FL#i : NVPTXReg<"%fd"#i>; // 64-bit float
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// Arguments
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def ia#i : NVPTXReg<"%ia"#i>;
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def la#i : NVPTXReg<"%la"#i>;
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def fa#i : NVPTXReg<"%fa"#i>;
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def da#i : NVPTXReg<"%da"#i>;
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}
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foreach i = 0-31 in {
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def ENVREG#i : NVPTXReg<"%envreg"#i>;
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}
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;
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def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>;
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def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 4))>;
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def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4))>;
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def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
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def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>;
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def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>;
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def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>;
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def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>;
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def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>;
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// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
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def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot,
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(sequence "ENVREG%u", 0, 31))>;
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