Sanjay Patel 7c0fa0cfab Correct a missing RUN line in the ARM codegen test for fneg ops. We should also explicitly specify +/-neonfp. ... The bug was introduced at r99570 when use of "-arm-use-neon-fp" was removed. Differential Revision: http://reviews.llvm.org/D4846 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215377 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-11 19:04:28 +00:00
..
AArch64	In Machine CSE pass, the source register of a COPY machine instruction can	2014-08-11 05:17:19 +00:00
ARM	Correct a missing RUN line in the ARM codegen test for fneg ops. We should also explicitly specify +/-neonfp.	2014-08-11 19:04:28 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Add support for scalarizing cttz_zero_undef	2014-08-10 22:49:54 +00:00
MSP430
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	Provide an implementation of getNoopForMachoTarget for PPC, otherwise	2014-08-08 19:13:23 +00:00
R600	R600/SI: Custom lower CONCAT_VECTORS	2014-08-09 01:06:56 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	[ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly	2014-08-02 05:40:40 +00:00
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[FastISel][X86] Fix INC/DEC optimization (r215230)	2014-08-08 18:47:04 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00