mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c2a4a30e0
1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
363 lines
12 KiB
C++
363 lines
12 KiB
C++
//===- PTXInstrInfo.cpp - PTX Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ptx-instrinfo"
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#include "PTX.h"
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#include "PTXInstrInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_INSTRINFO_CTOR
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#include "PTXGenInstrInfo.inc"
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using namespace llvm;
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PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
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: PTXGenInstrInfo(),
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RI(_TM, *this), TM(_TM) {}
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static const struct map_entry {
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const TargetRegisterClass *cls;
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const int opcode;
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} map[] = {
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{ &PTX::RegI16RegClass, PTX::MOVU16rr },
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{ &PTX::RegI32RegClass, PTX::MOVU32rr },
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{ &PTX::RegI64RegClass, PTX::MOVU64rr },
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{ &PTX::RegF32RegClass, PTX::MOVF32rr },
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{ &PTX::RegF64RegClass, PTX::MOVF64rr },
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{ &PTX::RegPredRegClass, PTX::MOVPREDrr }
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};
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void PTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const {
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const MachineRegisterInfo& MRI = MBB.getParent()->getRegInfo();
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//assert(MRI.getRegClass(SrcReg) == MRI.getRegClass(DstReg) &&
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// "Invalid register copy between two register classes");
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for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++i) {
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if (map[i].cls == MRI.getRegClass(DstReg)) {
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const MCInstrDesc &MCID = get(map[i].opcode);
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MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).
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addReg(SrcReg, getKillRegState(KillSrc));
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AddDefaultPredicate(MI);
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return;
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}
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}
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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bool PTXInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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if (DstRC != SrcRC)
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return false;
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for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i)
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if (DstRC == map[i].cls) {
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const MCInstrDesc &MCID = get(map[i].opcode);
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MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg);
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AddDefaultPredicate(MI);
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return true;
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}
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return false;
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}
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bool PTXInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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switch (MI.getOpcode()) {
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default:
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return false;
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case PTX::MOVU16rr:
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case PTX::MOVU32rr:
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case PTX::MOVU64rr:
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case PTX::MOVF32rr:
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case PTX::MOVF64rr:
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case PTX::MOVPREDrr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
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"Invalid register-register move instruction");
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SrcSubIdx = DstSubIdx = 0; // No sub-registers
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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// predicate support
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bool PTXInstrInfo::isPredicated(const MachineInstr *MI) const {
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int i = MI->findFirstPredOperandIdx();
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return i != -1 && MI->getOperand(i).getReg() != PTX::NoRegister;
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}
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bool PTXInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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return !isPredicated(MI) && get(MI->getOpcode()).isTerminator();
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}
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bool PTXInstrInfo::
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const {
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if (Pred.size() < 2)
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llvm_unreachable("lesser than 2 predicate operands are provided");
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int i = MI->findFirstPredOperandIdx();
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if (i == -1)
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llvm_unreachable("missing predicate operand");
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MI->getOperand(i).setReg(Pred[0].getReg());
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MI->getOperand(i+1).setImm(Pred[1].getImm());
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return true;
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}
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bool PTXInstrInfo::
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SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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const MachineOperand &PredReg1 = Pred1[0];
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const MachineOperand &PredReg2 = Pred2[0];
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if (PredReg1.getReg() != PredReg2.getReg())
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return false;
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const MachineOperand &PredOp1 = Pred1[1];
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const MachineOperand &PredOp2 = Pred2[1];
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if (PredOp1.getImm() != PredOp2.getImm())
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return false;
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return true;
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}
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bool PTXInstrInfo::
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DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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// If an instruction sets a predicate register, it defines a predicate.
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// TODO supprot 5-operand format of setp instruction
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if (MI->getNumOperands() < 1)
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return false;
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const MachineOperand &MO = MI->getOperand(0);
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if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::RegPredRegClass)
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return false;
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Pred.push_back(MO);
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Pred.push_back(MachineOperand::CreateImm(PTXPredicate::None));
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return true;
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}
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// branch support
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bool PTXInstrInfo::
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AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// TODO implement cases when AllowModify is true
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if (MBB.empty())
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return true;
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MachineBasicBlock::iterator iter = MBB.end();
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const MachineInstr& instLast1 = *--iter;
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const MCInstrDesc &desc1 = instLast1.getDesc();
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// for special case that MBB has only 1 instruction
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const bool IsSizeOne = MBB.size() == 1;
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// if IsSizeOne is true, *--iter and instLast2 are invalid
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// we put a dummy value in instLast2 and desc2 since they are used
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const MachineInstr& instLast2 = IsSizeOne ? instLast1 : *--iter;
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const MCInstrDesc &desc2 = IsSizeOne ? desc1 : instLast2.getDesc();
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DEBUG(dbgs() << "\n");
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DEBUG(dbgs() << "AnalyzeBranch: opcode: " << instLast1.getOpcode() << "\n");
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DEBUG(dbgs() << "AnalyzeBranch: MBB: " << MBB.getName().str() << "\n");
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DEBUG(dbgs() << "AnalyzeBranch: TBB: " << TBB << "\n");
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DEBUG(dbgs() << "AnalyzeBranch: FBB: " << FBB << "\n");
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// this block ends with no branches
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if (!IsAnyKindOfBranch(instLast1)) {
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DEBUG(dbgs() << "AnalyzeBranch: ends with no branch\n");
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return false;
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}
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// this block ends with only an unconditional branch
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if (desc1.isUnconditionalBranch() &&
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// when IsSizeOne is true, it "absorbs" the evaluation of instLast2
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(IsSizeOne || !IsAnyKindOfBranch(instLast2))) {
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DEBUG(dbgs() << "AnalyzeBranch: ends with only uncond branch\n");
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TBB = GetBranchTarget(instLast1);
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return false;
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}
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// this block ends with a conditional branch and
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// it falls through to a successor block
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if (desc1.isConditionalBranch() &&
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IsAnySuccessorAlsoLayoutSuccessor(MBB)) {
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DEBUG(dbgs() << "AnalyzeBranch: ends with cond branch and fall through\n");
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TBB = GetBranchTarget(instLast1);
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int i = instLast1.findFirstPredOperandIdx();
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Cond.push_back(instLast1.getOperand(i));
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Cond.push_back(instLast1.getOperand(i+1));
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return false;
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}
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// when IsSizeOne is true, we are done
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if (IsSizeOne)
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return true;
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// this block ends with a conditional branch
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// followed by an unconditional branch
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if (desc2.isConditionalBranch() &&
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desc1.isUnconditionalBranch()) {
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DEBUG(dbgs() << "AnalyzeBranch: ends with cond and uncond branch\n");
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TBB = GetBranchTarget(instLast2);
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FBB = GetBranchTarget(instLast1);
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int i = instLast2.findFirstPredOperandIdx();
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Cond.push_back(instLast2.getOperand(i));
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Cond.push_back(instLast2.getOperand(i+1));
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return false;
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}
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// branch cannot be understood
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DEBUG(dbgs() << "AnalyzeBranch: cannot be understood\n");
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return true;
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}
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unsigned PTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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unsigned count = 0;
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while (!MBB.empty())
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if (IsAnyKindOfBranch(MBB.back())) {
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MBB.pop_back();
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++count;
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} else
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break;
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DEBUG(dbgs() << "RemoveBranch: MBB: " << MBB.getName().str() << "\n");
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DEBUG(dbgs() << "RemoveBranch: remove " << count << " branch inst\n");
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return count;
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}
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unsigned PTXInstrInfo::
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InsertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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DEBUG(dbgs() << "InsertBranch: MBB: " << MBB.getName().str() << "\n");
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DEBUG(if (TBB) dbgs() << "InsertBranch: TBB: " << TBB->getName().str()
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<< "\n";
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else dbgs() << "InsertBranch: TBB: (NULL)\n");
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DEBUG(if (FBB) dbgs() << "InsertBranch: FBB: " << FBB->getName().str()
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<< "\n";
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else dbgs() << "InsertBranch: FBB: (NULL)\n");
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DEBUG(dbgs() << "InsertBranch: Cond size: " << Cond.size() << "\n");
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assert(TBB && "TBB is NULL");
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if (FBB) {
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BuildMI(&MBB, DL, get(PTX::BRAdp))
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.addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
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BuildMI(&MBB, DL, get(PTX::BRAd))
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.addMBB(FBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
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return 2;
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} else if (Cond.size()) {
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BuildMI(&MBB, DL, get(PTX::BRAdp))
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.addMBB(TBB).addReg(Cond[0].getReg()).addImm(Cond[1].getImm());
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return 1;
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} else {
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BuildMI(&MBB, DL, get(PTX::BRAd))
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.addMBB(TBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
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return 1;
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}
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}
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// Memory operand folding for spills
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void PTXInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MII,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert(false && "storeRegToStackSlot should not be called for PTX");
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}
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void PTXInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MII,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert(false && "loadRegFromStackSlot should not be called for PTX");
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}
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// static helper routines
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MachineSDNode *PTXInstrInfo::
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GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
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DebugLoc dl, EVT VT, SDValue Op1) {
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SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
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SDValue predOp = DAG->getTargetConstant(PTXPredicate::None, MVT::i32);
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SDValue ops[] = { Op1, predReg, predOp };
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return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops));
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}
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MachineSDNode *PTXInstrInfo::
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GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
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DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) {
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SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
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SDValue predOp = DAG->getTargetConstant(PTXPredicate::None, MVT::i32);
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SDValue ops[] = { Op1, Op2, predReg, predOp };
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return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops));
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}
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void PTXInstrInfo::AddDefaultPredicate(MachineInstr *MI) {
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if (MI->findFirstPredOperandIdx() == -1) {
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MI->addOperand(MachineOperand::CreateReg(PTX::NoRegister, /*IsDef=*/false));
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MI->addOperand(MachineOperand::CreateImm(PTXPredicate::None));
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}
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}
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bool PTXInstrInfo::IsAnyKindOfBranch(const MachineInstr& inst) {
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const MCInstrDesc &desc = inst.getDesc();
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return desc.isTerminator() || desc.isBranch() || desc.isIndirectBranch();
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}
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bool PTXInstrInfo::
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IsAnySuccessorAlsoLayoutSuccessor(const MachineBasicBlock& MBB) {
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for (MachineBasicBlock::const_succ_iterator
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i = MBB.succ_begin(), e = MBB.succ_end(); i != e; ++i)
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if (MBB.isLayoutSuccessor((const MachineBasicBlock*) &*i))
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return true;
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return false;
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}
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MachineBasicBlock *PTXInstrInfo::GetBranchTarget(const MachineInstr& inst) {
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// FIXME So far all branch instructions put destination in 1st operand
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const MachineOperand& target = inst.getOperand(0);
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assert(target.isMBB() && "FIXME: detect branch target operand");
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return target.getMBB();
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}
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