mirror of
https://github.com/c64scene-ar/llvm-6502.git
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929bdb2379
By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
154 lines
4.4 KiB
LLVM
154 lines
4.4 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s
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; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-V8 %s
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; rdar://13782395
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define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
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; CHECK-LABEL: t1:
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; CHECK: Block address taken
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; CHECK-NOT: Address of block that was removed by CodeGen
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store i8* blockaddress(@t1, %cond_true), i8** %retaddr
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%tmp2 = icmp eq i32 %a, 0
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br i1 %tmp2, label %cond_false, label %cond_true
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cond_true:
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%tmp5 = add i32 %b, 1
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ret i32 %tmp5
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cond_false:
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%tmp7 = add i32 %b, -1
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ret i32 %tmp7
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
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; CHECK-LABEL: t2:
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; CHECK: Block address taken
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; CHECK: %cond_true
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; CHECK: add
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; CHECK: bx lr
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store i8* blockaddress(@t2, %cond_true), i8** %retaddr
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%tmp2 = icmp sgt i32 %c, 10
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%tmp5 = icmp slt i32 %d, 4
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%tmp8 = and i1 %tmp5, %tmp2
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%tmp13 = add i32 %b, %a
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br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
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cond_true:
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%tmp15 = add i32 %tmp13, %c
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%tmp1821 = sub i32 %tmp15, %d
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ret i32 %tmp1821
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UnifiedReturnBlock:
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ret i32 %tmp13
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}
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define hidden fastcc void @t3(i8** %retaddr) {
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; CHECK-LABEL: t3:
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; CHECK: Block address taken
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; CHECK-NOT: Address of block that was removed by CodeGen
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bb:
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store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr
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br i1 undef, label %bb77, label %bb7.i
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bb7.i: ; preds = %bb35
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br label %bb2.i
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KBBlockZero_return_1: ; preds = %KBBlockZero.exit
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unreachable
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KBBlockZero_return_0: ; preds = %KBBlockZero.exit
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unreachable
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bb77: ; preds = %bb26, %bb12, %bb
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ret void
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bb2.i: ; preds = %bb6.i350, %bb7.i
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br i1 undef, label %bb6.i350, label %KBBlockZero.exit
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bb6.i350: ; preds = %bb2.i
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br label %bb2.i
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KBBlockZero.exit: ; preds = %bb2.i
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indirectbr i8* undef, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
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}
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; If-converter was checking for the wrong predicate subsumes pattern when doing
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; nested predicates.
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; E.g., Let A be a basic block that flows conditionally into B and B be a
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; predicated block.
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; B can be predicated with A.BrToBPredicate into A iff B.Predicate is less
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; "permissive" than A.BrToBPredicate, i.e., iff A.BrToBPredicate subsumes
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; B.Predicate.
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; <rdar://problem/14379453>
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; Hard-coded registers comes from the ABI.
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; CHECK-LABEL: wrapDistance:
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; CHECK: cmp r1, #59
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; CHECK-NEXT: itt le
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; CHECK-NEXT: suble r0, r2, #1
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; CHECK-NEXT: bxle lr
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; CHECK-NEXT: subs [[REG:r[0-9]+]], #120
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; CHECK-NEXT: cmp [[REG]], r1
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; CHECK-NOT: it lt
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; CHECK-NEXT: bge [[LABEL:.+]]
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; Next BB
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; CHECK-NOT: cmplt
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; CHECK: cmp r0, #119
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; CHECK-NEXT: itt le
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; CHECK-NEXT: addle r0, r1, #1
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; CHECK-NEXT: bxle lr
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; Next BB
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; CHECK: [[LABEL]]:
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; CHECK-NEXT: subs r0, r1, r0
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; CHECK-NEXT: bx lr
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; CHECK-V8-LABEL: wrapDistance:
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; CHECK-V8: cmp r1, #59
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; CHECK-V8-NEXT: bgt
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; CHECK-V8-NEXT: %if.then
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; CHECK-V8-NEXT: subs r0, r2, #1
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; CHECK-V8-NEXT: bx lr
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; CHECK-V8-NEXT: %if.else
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; CHECK-V8-NEXT: subs [[REG:r[0-9]+]], #120
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; CHECK-V8-NEXT: cmp [[REG]], r1
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; CHECK-V8-NEXT: bge
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; CHECK-V8-NEXT: %if.else
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; CHECK-V8-NEXT: cmp r0, #119
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; CHECK-V8-NEXT: bgt
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; CHECK-V8-NEXT: %if.then4
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; CHECK-V8-NEXT: adds r0, r1, #1
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; CHECK-V8-NEXT: bx lr
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; CHECK-V8-NEXT: %if.end5
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; CHECK-V8-NEXT: subs r0, r1, r0
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; CHECK-V8-NEXT: bx lr
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define i32 @wrapDistance(i32 %tx, i32 %sx, i32 %w) {
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entry:
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%cmp = icmp slt i32 %sx, 60
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%sub = add nsw i32 %w, -1
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br label %return
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if.else: ; preds = %entry
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%sub1 = add nsw i32 %w, -120
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%cmp2 = icmp slt i32 %sub1, %sx
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%cmp3 = icmp slt i32 %tx, 120
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%or.cond = and i1 %cmp2, %cmp3
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br i1 %or.cond, label %if.then4, label %if.end5
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if.then4: ; preds = %if.else
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%add = add nsw i32 %sx, 1
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br label %return
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if.end5: ; preds = %if.else
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%sub6 = sub nsw i32 %sx, %tx
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br label %return
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return: ; preds = %if.end5, %if.then4, %if.then
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%retval.0 = phi i32 [ %sub, %if.then ], [ %add, %if.then4 ], [ %sub6, %if.end5 ]
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ret i32 %retval.0
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}
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