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7c3234c6be
works with. SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering objects now get created once per SelectionDAGISel instance, and can be reused across blocks and across functions. Previously, they were created and destroyed each time they were needed. This reorganization simplifies the handling of PHI nodes, and also SwitchCases, JumpTables, and BitTestBlocks. This simplification has the side effect of fixing a bug in FastISel where successor PHI nodes weren't being updated correctly. This is also a step towards making the transition from FastISel into and out of SelectionDAG faster, and also making plain SelectionDAG faster on code with lots of little blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55450 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
4.1 KiB
C++
130 lines
4.1 KiB
C++
//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#include "llvm/BasicBlock.h"
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#include "llvm/Pass.h"
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#include "llvm/Constant.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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class SelectionDAGLowering;
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class SDValue;
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class MachineRegisterInfo;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class TargetLowering;
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class FunctionLoweringInfo;
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class HazardRecognizer;
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class GCFunctionInfo;
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class ScheduleDAG;
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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class SelectionDAGISel : public FunctionPass {
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public:
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TargetLowering &TLI;
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MachineRegisterInfo *RegInfo;
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FunctionLoweringInfo *FuncInfo;
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SelectionDAG *CurDAG;
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SelectionDAGLowering *SDL;
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MachineBasicBlock *BB;
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AliasAnalysis *AA;
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GCFunctionInfo *GFI;
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bool Fast;
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std::vector<SDNode*> TopOrder;
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static char ID;
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explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
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virtual ~SelectionDAGISel();
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TargetLowering &getTargetLowering() { return TLI; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual bool runOnFunction(Function &Fn);
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unsigned MakeReg(MVT VT);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelect() = 0;
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virtual void InstructionSelectPostProcessing() {}
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void SelectRootInit() {
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DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
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}
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/// SelectInlineAsmMemoryOperand - Select the specified address as a target
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/// addressing mode, according to the specified constraint code. If this does
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/// not match or is not implemented, return true. The resultant operands
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/// (which will appear in the machine instruction) should be added to the
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/// OutOps vector.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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return true;
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}
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/// CanBeFoldedBy - Returns true if the specific operand node N of U can be
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/// folded during instruction selection that starts at Root?
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virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
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return true;
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}
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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/// to use for this target when scheduling the DAG.
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virtual HazardRecognizer *CreateTargetHazardRecognizer();
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protected:
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/// DAGSize - Size of DAG being instruction selected.
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///
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unsigned DAGSize;
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
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// Calls to these predicates are generated by tblgen.
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bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
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int64_t DesiredMaskS) const;
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bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
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int64_t DesiredMaskS) const;
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private:
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void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF);
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void FinishBasicBlock();
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void SelectBasicBlock(BasicBlock *LLVMBB,
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BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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bool DoArgs);
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void CodeGenAndEmitDAG();
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void LowerArguments(BasicBlock *BB);
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void ComputeLiveOutVRegInfo();
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void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
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/// Pick a safe ordering for instructions for each target node in the
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/// graph.
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ScheduleDAG *Schedule();
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};
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}
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#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
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