Robert Lytton 7c739380ee XCore target: change to Sched::Source ... This sidesteps a bug in PrescheduleNodesWithMultipleUses() which does not check if callResources will be affected by the transformation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190299 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-09 10:42:05 +00:00
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AArch64	Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,	2013-09-09 02:20:27 +00:00
ARM	Debug Info Testing: update context from empty string to null.	2013-09-08 03:11:54 +00:00
CPP	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Generic	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Hexagon	Debug Info Testing: use null instead of an empty string in context field.	2013-09-09 00:12:17 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	[mips] Fix typos.	2013-09-07 01:14:42 +00:00
MSP430	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
NVPTX	[NVPTX] Re-enable assembly printing support for inline assembly	2013-08-24 01:17:23 +00:00
PowerPC	Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.	2013-09-06 21:03:58 +00:00
R600	R600: Add support for LDS atomic subtract	2013-09-06 20:17:42 +00:00
SPARC	[Sparc] Correctly handle call to functions with ReturnsTwice attribute.	2013-09-05 05:32:16 +00:00
SystemZ	[SystemZ] Tweak integer comparison code	2013-09-06 11:51:39 +00:00
Thumb	ARM: Use "dmb sy" for barriers on M-class CPUs	2013-08-28 14:39:19 +00:00
Thumb2	ARM: make sure ARM-mode pseudo-inst requires IsARM	2013-08-23 10:16:39 +00:00
X86	Generate compact unwind encoding from CFI directives.	2013-09-09 02:37:14 +00:00
XCore	XCore target: change to Sched::Source	2013-09-09 10:42:05 +00:00