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The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191071 91177308-0d34-0410-b5e6-96231b3b80d8
205 lines
6.6 KiB
C++
205 lines
6.6 KiB
C++
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Hexagon target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Transforms/IPO/PassManagerBuilder.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon MI Scheduling"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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/// things to work on Win32 without this. Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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extern "C" void LLVMInitializeHexagonTarget() {
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// Register the target.
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RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
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}
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static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
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return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler());
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}
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static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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///
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/// Hexagon_TODO: Do I need an aggregate alignment?
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///
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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DL("e-p:32:32:32-"
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"i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
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"f64:64:64-f32:32:32-a0:0-n32") ,
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Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
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TSInfo(*this),
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FrameLowering(Subtarget),
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InstrItins(&Subtarget.getInstrItineraryData()) {
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setMCUseCFI(false);
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initAsmInfo();
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}
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// addPassesForOptimizations - Allow the backend (target) to add Target
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// Independent Optimization passes to the Pass Manager.
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bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
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if (getOptLevel() != CodeGenOpt::None) {
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PM.add(createConstantPropagationPass());
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PM.add(createLoopSimplifyPass());
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PM.add(createDeadCodeEliminationPass());
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PM.add(createConstantPropagationPass());
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PM.add(createLoopUnrollPass());
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PM.add(createLoopStrengthReducePass());
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}
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return true;
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}
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
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class HexagonPassConfig : public TargetPassConfig {
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public:
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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// FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
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// HexagonSubtarget::enableMachineScheduler() { return true; }.
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// That will bypass the SelectionDAG VLIW scheduler, which is probably just
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// hurting compile time and will be removed eventually anyway.
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if (DisableHexagonMISched)
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disablePass(&MachineSchedulerID);
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else
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enablePass(&MachineSchedulerID);
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}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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}
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virtual ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const {
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return createVLIWMachineSched(C);
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}
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virtual bool addInstSelector();
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virtual bool addPreRegAlloc();
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virtual bool addPostRegAlloc();
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virtual bool addPreSched2();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new HexagonPassConfig(this, PM);
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}
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bool HexagonPassConfig::addInstSelector() {
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HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonRemoveExtendArgs(TM));
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addPass(createHexagonISelDag(TM, getOptLevel()));
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if (!NoOpt) {
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addPass(createHexagonPeephole());
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printAndVerify("After hexagon peephole pass");
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}
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return false;
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}
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bool HexagonPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableHardwareLoops)
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addPass(createHexagonHardwareLoops());
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return false;
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}
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bool HexagonPassConfig::addPostRegAlloc() {
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableHexagonCFGOpt)
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addPass(createHexagonCFGOptimizer(TM));
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return false;
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}
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bool HexagonPassConfig::addPreSched2() {
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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const HexagonTargetObjectFile &TLOF =
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(const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering();
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addPass(createHexagonCopyToCombine());
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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if (!TLOF.IsSmallDataEnabled()) {
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addPass(createHexagonSplitConst32AndConst64(TM));
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printAndVerify("After hexagon split const32/64 pass");
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}
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return true;
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}
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bool HexagonPassConfig::addPreEmitPass() {
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonNewValueJump());
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// Expand Spill code for predicate registers.
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addPass(createHexagonExpandPredSpillCode(TM));
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// Split up TFRcondsets into conditional transfers.
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addPass(createHexagonSplitTFRCondSets(TM));
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// Create Packets.
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if (!NoOpt) {
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if (!DisableHardwareLoops)
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addPass(createHexagonFixupHwLoops());
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addPass(createHexagonPacketizer());
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}
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return false;
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}
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