Jim Grosbach b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. ... The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-19 22:45:10 +00:00
..
arm-tests.txt	Tweak ARM assembly parsing and printing of MSR instruction.	2011-07-19 22:45:10 +00:00
dg.exp
invalid-Bcc-thumb.txt
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt
invalid-DSB-arm.txt
invalid-LDC-form-arm.txt
invalid-LDR_POST-arm.txt
invalid-LDR_PRE-arm.txt
invalid-LDRB_POST-arm.txt
invalid-LDRD_PRE-thumb.txt
invalid-LDRrs-arm.txt
invalid-LDRT-arm.txt
invalid-LSL-regform.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-RSC-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-SSAT-arm.txt
invalid-STMIA_UPD-thumb.txt
invalid-STRBrs-arm.txt
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt
invalid-t2LDRBT-thumb.txt
invalid-t2LDREXD-thumb.txt
invalid-t2LDRSHi8-thumb.txt
invalid-t2LDRSHi12-thumb.txt
invalid-t2STR_POST-thumb.txt
invalid-t2STRD_PRE-thumb.txt
invalid-t2STREXB-thumb.txt
invalid-t2STREXD-thumb.txt
invalid-UMAAL-arm.txt
invalid-UQADD8-arm.txt
invalid-VLD1DUPq8_UPD-arm.txt
invalid-VLD3DUPd32_UPD-thumb.txt
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt
invalid-VST2b32_UPD-arm.txt
neon-tests.txt
thumb-printf.txt
thumb-tests.txt	Tweak ARM assembly parsing and printing of MSR instruction.	2011-07-19 22:45:10 +00:00