NAKAMURA Takumi 7cd85b7492 llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188340 91177308-0d34-0410-b5e6-96231b3b80d8

2013-08-14 00:46:00 +00:00

..

AArch64

CHECK-LABEL-ify tests

2013-08-09 17:50:15 +00:00

ARM

DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)

2013-08-13 21:30:58 +00:00

CPP

…

Generic

…

Hexagon

Refactor isInTailCallPosition handling

2013-08-06 09:12:35 +00:00

Inputs

Debug Info Verifier: verify SPs in llvm.dbg.sp.

2013-07-27 01:26:08 +00:00

Mips

[mips] Properly parse registers that appear in inline-asm constraints.

2013-08-14 00:21:25 +00:00

MSP430

Use conventional syntax for branches.

2013-07-14 18:19:44 +00:00

NVPTX

[NVPTX] Add missing patterns for i1 [s,u]int_to_fp

2013-08-06 14:13:34 +00:00

PowerPC

Fix FileCheck --check-prefix lines.

2013-08-12 12:43:26 +00:00

R600

R600: Set scheduling preference to Sched::Source

2013-08-12 22:33:21 +00:00

SI

…

SPARC

Allocate local registers in order for optimal coloring.

2013-07-25 18:35:14 +00:00

SystemZ

[SystemZ] Use CLC and IPM to implement memcmp

2013-08-12 10:28:10 +00:00

Thumb

Debug Info: update testing cases to pass verifier.

2013-07-29 18:12:58 +00:00

Thumb2

Refactor AnalyzeBranch on ARM. The previous version did not always analyze

2013-07-19 23:52:47 +00:00

X86

llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.

2013-08-14 00:46:00 +00:00

XCore

XCore target: Fix Vararg handling

2013-08-01 08:29:44 +00:00