llvm-6502/test/CodeGen/R600/atomic_load_sub.ll
Matt Arsenault 9c0b2d08d3 R600/SI: Don't display the GDS bit.
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204270 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 22:19:43 +00:00

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810 B
LLVM

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK-LABEL: @atomic_sub_local
; R600-CHECK: LDS_SUB *
; SI-CHECK-LABEL: @atomic_sub_local
; SI-CHECK: DS_SUB_U32_RTN
define void @atomic_sub_local(i32 addrspace(3)* %local) {
entry:
%0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
ret void
}
; R600-CHECK-LABEL: @atomic_sub_ret_local
; R600-CHECK: LDS_SUB_RET *
; SI-CHECK-LABEL: @atomic_sub_ret_local
; SI-CHECK: DS_SUB_U32_RTN
define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
entry:
%0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
store i32 %0, i32 addrspace(1)* %out
ret void
}