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https://github.com/c64scene-ar/llvm-6502.git
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3c14ba5962
DAGCombiner could fold (truncate (load)) -> smaller load if the original load was the width of the truncation result or wider. This patch extends it to handle cases where the original load was narrower (and so the extension type stays the same). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197030 91177308-0d34-0410-b5e6-96231b3b80d8
195 lines
4.5 KiB
LLVM
195 lines
4.5 KiB
LLVM
; Test insertions of i32s into the low half of an i64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Insertion of an i32 can be done using LR.
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define i64 @f1(i64 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%low = zext i32 %b to i64
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%high = and i64 %a, -4294967296
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%res = or i64 %high, %low
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ret i64 %res
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}
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; ... and again with the operands reversed.
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define i64 @f2(i64 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%low = zext i32 %b to i64
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%high = and i64 %a, -4294967296
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%res = or i64 %low, %high
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ret i64 %res
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}
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; Like f1, but with "in register" zero extension.
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define i64 @f3(i64 %a, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%low = and i64 %b, 4294967295
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%high = and i64 %a, -4294967296
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%res = or i64 %high, %low
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ret i64 %res
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}
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; ... and again with the operands reversed.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%low = and i64 %b, 4294967295
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%high = and i64 %a, -4294967296
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%res = or i64 %low, %high
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ret i64 %res
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}
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; Unary operations can be done directly into the low half.
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define i64 @f5(i64 %a, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lcr %r2, %r3
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; CHECK: br %r14
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%neg = sub i32 0, %b
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%low = zext i32 %neg to i64
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%high = and i64 %a, -4294967296
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%res = or i64 %high, %low
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ret i64 %res
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}
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; ...likewise three-operand binary operations like RLL.
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define i64 @f6(i64 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: rll %r2, %r3, 1
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; CHECK: br %r14
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%parta = shl i32 %b, 1
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%partb = lshr i32 %b, 31
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%rot = or i32 %parta, %partb
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%low = zext i32 %rot to i64
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%high = and i64 %a, -4294967296
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%res = or i64 %low, %high
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ret i64 %res
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}
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; Loads can be done directly into the low half. The range of L is checked
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; in the move tests.
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define i64 @f7(i64 %a, i32 *%src) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: l %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i32 *%src
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%low = zext i32 %b to i64
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%high = and i64 %a, -4294967296
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%res = or i64 %high, %low
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ret i64 %res
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}
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; ...likewise extending loads.
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define i64 @f8(i64 %a, i8 *%src) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lb %r2, 0(%r3)
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; CHECK: br %r14
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%byte = load i8 *%src
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%b = sext i8 %byte to i32
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%low = zext i32 %b to i64
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%high = and i64 %a, -4294967296
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%res = or i64 %high, %low
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ret i64 %res
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}
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; Check a case like f1 in which there is no AND. We simply know from context
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; that the upper half of one OR operand and the lower half of the other are
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; both clear.
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define i64 @f9(i64 %a, i32 %b) {
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; CHECK-LABEL: f9:
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; CHECK: sllg %r2, %r2, 32
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%shift = shl i64 %a, 32
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%low = zext i32 %b to i64
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%or = or i64 %shift, %low
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ret i64 %or
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}
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; ...and again with the operands reversed.
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define i64 @f10(i64 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: sllg %r2, %r2, 32
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%shift = shl i64 %a, 32
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%low = zext i32 %b to i64
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%or = or i64 %low, %shift
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ret i64 %or
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}
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; Like f9, but with "in register" zero extension.
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define i64 @f11(i64 %a, i64 %b) {
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; CHECK-LABEL: f11:
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%shift = shl i64 %a, 32
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%low = and i64 %b, 4294967295
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%or = or i64 %shift, %low
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ret i64 %or
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}
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; ...and again with the operands reversed.
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define i64 @f12(i64 %a, i64 %b) {
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; CHECK-LABEL: f12:
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%shift = shl i64 %a, 32
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%low = and i64 %b, 4294967295
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%or = or i64 %low, %shift
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ret i64 %or
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}
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; Like f9, but for larger shifts than 32.
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define i64 @f13(i64 %a, i32 %b) {
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; CHECK-LABEL: f13:
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; CHECK: sllg %r2, %r2, 60
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; CHECK: lr %r2, %r3
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; CHECK: br %r14
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%shift = shl i64 %a, 60
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%low = zext i32 %b to i64
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%or = or i64 %shift, %low
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ret i64 %or
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}
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; We previously wrongly removed the upper AND as dead.
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define i64 @f14(i64 %a, i64 %b) {
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; CHECK-LABEL: f14:
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; CHECK: risbg {{%r[0-5]}}, %r2, 6, 134, 0
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; CHECK: br %r14
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%and1 = and i64 %a, 144115188075855872
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%and2 = and i64 %b, 15
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%or = or i64 %and1, %and2
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%res = icmp eq i64 %or, 0
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%ext = sext i1 %res to i64
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ret i64 %ext
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}
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; Check another representation of f8.
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define i64 @f15(i64 %a, i8 *%src) {
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; CHECK-LABEL: f15:
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; CHECK-NOT: {{%r[23]}}
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; CHECK: lb %r2, 0(%r3)
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; CHECK: br %r14
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%byte = load i8 *%src
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%b = sext i8 %byte to i64
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%low = and i64 %b, 4294967295
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%high = and i64 %a, -4294967296
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%res = or i64 %high, %low
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ret i64 %res
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}
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