llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-24 06:30:19 +00:00

History

Nate Begeman 7cee81703d Add support to tablegen for naming the nodes themselves, not just the operands, in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite, and as it turns out, cleans up a hack in the Alpha instruction info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8		2009-03-19 05:21:56 +00:00
..
AsmPrinter	It makes no sense to have a ODR version of common	2009-03-11 20:14:15 +00:00
Alpha.h	Overhaul my earlier submission due to feedback. It's a large patch, but most of	2009-02-24 08:30:20 +00:00
Alpha.td
AlphaBranchSelector.cpp
AlphaCodeEmitter.cpp
AlphaInstrFormats.td
AlphaInstrInfo.cpp	Factor out the code to add a MachineOperand to a MachineInstrBuilder.	2009-02-18 05:45:50 +00:00
AlphaInstrInfo.h	Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty	2009-02-09 07:14:22 +00:00
AlphaInstrInfo.td	Add support to tablegen for naming the nodes themselves, not just the operands,	2009-03-19 05:21:56 +00:00
AlphaISelDAGToDAG.cpp	Remove non-DebugLoc forms of CopyToReg and CopyFromReg.	2009-02-04 23:02:30 +00:00
AlphaISelLowering.cpp	Remove non-DebugLoc versions of BuildMI from Alpha and Cell.	2009-02-13 02:30:42 +00:00
AlphaISelLowering.h	Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing	2009-02-07 16:15:20 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp	Remove non-DebugLoc versions of BuildMI from Alpha and Cell.	2009-02-13 02:30:42 +00:00
AlphaRegisterInfo.cpp	Propagate debug loc info through prologue/epilogue.	2009-02-23 00:42:30 +00:00
AlphaRegisterInfo.h
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetAsmInfo.cpp
AlphaTargetAsmInfo.h
AlphaTargetMachine.cpp	Overhaul my earlier submission due to feedback. It's a large patch, but most of	2009-02-24 08:30:20 +00:00
AlphaTargetMachine.h
CMakeLists.txt
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html