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02d711b93e
instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
67 lines
2.1 KiB
TableGen
67 lines
2.1 KiB
TableGen
//===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the STI Cell SPU target machine.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "llvm/Target/Target.td"
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// Holder of code fragments (you'd think this'd already be in
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// a td file somewhere... :-)
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class CodeFrag<dag frag> {
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dag Fragment = frag;
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}
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "SPURegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction formats, instructions
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//===----------------------------------------------------------------------===//
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include "SPUNodes.td"
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include "SPUOperands.td"
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include "SPUSchedule.td"
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include "SPUInstrFormats.td"
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include "SPUInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// Subtarget features:
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//===----------------------------------------------------------------------===//
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def DefaultProc: SubtargetFeature<"", "ProcDirective", "SPU::DEFAULT_PROC", "">;
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def LargeMemFeature:
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SubtargetFeature<"large_mem","UseLargeMem", "true",
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"Use large (>256) LSA memory addressing [default = false]">;
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def SPURev0 : Processor<"v0", SPUItineraries, [DefaultProc]>;
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//===----------------------------------------------------------------------===//
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// Calling convention:
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//===----------------------------------------------------------------------===//
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include "SPUCallingConv.td"
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// Target:
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def SPUInstrInfo : InstrInfo {
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let isLittleEndianEncoding = 1;
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}
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def SPU : Target {
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let InstructionSet = SPUInstrInfo;
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}
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