mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-29 11:29:39 +00:00
d1b7382983
CopyToReg/CopyFromReg/INLINEASM. These are annoying because
they have the same opcode before an after isel. Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.
With that done, give IsLegalToFold a new flag that causes it to
ignore chains. This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing. This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.
I currently #if out the dead code in the X86 backend and MSP
backend, I'll remove it for real in a follow-on patch.
The testcase changes are:
test/CodeGen/X86/sse3.ll: we generate better code
test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was
miscompiling this before, we now generate correct code
Convert it to filecheck while I'm at it.
test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
folding to make anton happy. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97596 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
1.6 KiB
LLVM
70 lines
1.6 KiB
LLVM
; RUN: llc -march=msp430 -combiner-alias-analysis < %s | FileCheck %s
|
|
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
|
|
target triple = "msp430-generic-generic"
|
|
@foo = common global i16 0, align 2
|
|
@bar = common global i16 0, align 2
|
|
|
|
define void @mov() nounwind {
|
|
; CHECK: mov:
|
|
; CHECK: mov.w &bar, &foo
|
|
%1 = load i16* @bar
|
|
store i16 %1, i16* @foo
|
|
ret void
|
|
}
|
|
|
|
define void @add() nounwind {
|
|
; CHECK: add:
|
|
; CHECK: add.w &bar, &foo
|
|
%1 = load i16* @bar
|
|
%2 = load i16* @foo
|
|
%3 = add i16 %2, %1
|
|
store i16 %3, i16* @foo
|
|
ret void
|
|
}
|
|
|
|
define void @and() nounwind {
|
|
; CHECK: and:
|
|
; CHECK: and.w &bar, &foo
|
|
%1 = load i16* @bar
|
|
%2 = load i16* @foo
|
|
%3 = and i16 %2, %1
|
|
store i16 %3, i16* @foo
|
|
ret void
|
|
}
|
|
|
|
define void @bis() nounwind {
|
|
; CHECK: bis:
|
|
; CHECK: bis.w &bar, &foo
|
|
%1 = load i16* @bar
|
|
%2 = load i16* @foo
|
|
%3 = or i16 %2, %1
|
|
store i16 %3, i16* @foo
|
|
ret void
|
|
}
|
|
|
|
define void @xor() nounwind {
|
|
; CHECK: xor:
|
|
; CHECK: xor.w &bar, &foo
|
|
%1 = load i16* @bar
|
|
%2 = load i16* @foo
|
|
%3 = xor i16 %2, %1
|
|
store i16 %3, i16* @foo
|
|
ret void
|
|
}
|
|
|
|
define i16 @mov2() nounwind {
|
|
entry:
|
|
%retval = alloca i16 ; <i16*> [#uses=3]
|
|
%x = alloca i32, align 2 ; <i32*> [#uses=1]
|
|
%y = alloca i32, align 2 ; <i32*> [#uses=1]
|
|
store i16 0, i16* %retval
|
|
%tmp = load i32* %y ; <i32> [#uses=1]
|
|
store i32 %tmp, i32* %x
|
|
store i16 0, i16* %retval
|
|
%0 = load i16* %retval ; <i16> [#uses=1]
|
|
ret i16 %0
|
|
; CHECK: mov2:
|
|
; CHECK: mov.w 0(r1), 4(r1)
|
|
; CHECK: mov.w 2(r1), 6(r1)
|
|
}
|