Daniel Sanders 7cfd0ffb3b [mips] Add cache and pref instructions ... Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-13 13:15:59 +00:00
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invalid-mips64r2-xfail.s	[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them	2014-05-13 11:45:36 +00:00
invalid-mips64r2.s	[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2	2014-05-14 15:35:03 +00:00
valid-xfail.s	[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS.	2014-05-08 15:17:29 +00:00
valid.s	[mips] Add cache and pref instructions	2014-06-13 13:15:59 +00:00