Preston Gurd 7d03cc8715 Verify that llvm can generate the prefetchw instruction when the CPU is ...

Atom Silvermont.

Patch by Sriram Murali.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190957 91177308-0d34-0410-b5e6-96231b3b80d8

2013-09-18 21:08:09 +00:00

..

AArch64

Implement 3 AArch64 neon instructions : umov smov ins.

2013-09-17 02:21:02 +00:00

ARM

[SelectionDAG] Teach the vector scalarizer about TRUNCATE.

2013-09-17 00:26:56 +00:00

CPP

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

Generic

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

Hexagon

Debug Info Testing: use null instead of an empty string in context field.

2013-09-09 00:12:17 +00:00

Inputs

Debug Info: add an identifier field to DICompositeType.

2013-08-26 22:39:55 +00:00

Mips

Expand the mask capability for deciding which functions are mips16 and mips32

2013-09-15 02:09:08 +00:00

MSP430

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

NVPTX

[NVPTX] Re-enable assembly printing support for inline assembly

2013-08-24 01:17:23 +00:00

PowerPC

[PowerPC] Fix problems with large code model (PR17169).

2013-09-17 20:03:25 +00:00

R600

R600: Move code handling literal folding into R600ISelLowering.

2013-09-12 23:44:53 +00:00

SPARC

[Sparc] Correctly handle call to functions with ReturnsTwice attribute.

2013-09-05 05:32:16 +00:00

SystemZ

[SystemZ] Add unsigned compare-and-branch instructions

2013-09-18 09:56:40 +00:00

Thumb

ARM: Use "dmb sy" for barriers on M-class CPUs

2013-08-28 14:39:19 +00:00

Thumb2

[ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.

2013-09-09 14:21:49 +00:00

X86

Verify that llvm can generate the prefetchw instruction when the CPU is

2013-09-18 21:08:09 +00:00

XCore

XCore handling of thread local lowering

2013-09-09 10:42:11 +00:00