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1bfa80359e
These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189972 91177308-0d34-0410-b5e6-96231b3b80d8
712 lines
24 KiB
C++
712 lines
24 KiB
C++
//=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The Cortex-A15 processor employs a tracking scheme in its register renaming
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// in order to process each instruction's micro-ops speculatively and
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// out-of-order with appropriate forwarding. The ARM architecture allows VFP
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// instructions to read and write 32-bit S-registers. Each S-register
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// corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
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//
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// There are several instruction patterns which can be used to provide this
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// capability which can provide higher performance than other, potentially more
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// direct patterns, specifically around when one micro-op reads a D-register
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// operand that has recently been written as one or more S-register results.
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//
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// This file defines a pre-regalloc pass which looks for SPR producers which
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// are going to be used by a DPR (or QPR) consumers and creates the more
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// optimized access pattern.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "a15-sd-optimizer"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "ARMISelLowering.h"
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#include "ARMTargetMachine.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <set>
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using namespace llvm;
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namespace {
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struct A15SDOptimizer : public MachineFunctionPass {
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static char ID;
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A15SDOptimizer() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM A15 S->D optimizer";
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}
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private:
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const ARMBaseInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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bool runOnInstruction(MachineInstr *MI);
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//
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// Instruction builder helpers
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//
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unsigned createDupLane(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned Reg, unsigned Lane,
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bool QPR=false);
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unsigned createExtractSubreg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned DReg, unsigned Lane,
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const TargetRegisterClass *TRC);
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unsigned createVExt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned Ssub0, unsigned Ssub1);
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unsigned createRegSequence(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned Reg1, unsigned Reg2);
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unsigned createInsertSubreg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL, unsigned DReg, unsigned Lane,
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unsigned ToInsert);
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unsigned createImplicitDef(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL);
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//
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// Various property checkers
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//
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bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
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bool hasPartialWrite(MachineInstr *MI);
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SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
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unsigned getDPRLaneFromSPR(unsigned SReg);
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//
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// Methods used for getting the definitions of partial registers
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//
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MachineInstr *elideCopies(MachineInstr *MI);
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void elideCopiesAndPHIs(MachineInstr *MI,
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SmallVectorImpl<MachineInstr*> &Outs);
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//
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// Pattern optimization methods
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//
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unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
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unsigned optimizeSDPattern(MachineInstr *MI);
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unsigned getPrefSPRLane(unsigned SReg);
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//
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// Sanitizing method - used to make sure if don't leave dead code around.
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//
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void eraseInstrWithNoUses(MachineInstr *MI);
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//
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// A map used to track the changes done by this pass.
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//
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std::map<MachineInstr*, unsigned> Replacements;
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std::set<MachineInstr *> DeadInstr;
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};
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char A15SDOptimizer::ID = 0;
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} // end anonymous namespace
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// Returns true if this is a use of a SPR register.
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bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
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const TargetRegisterClass *TRC) {
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if (!MO.isReg())
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return false;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
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else
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return TRC->contains(Reg);
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}
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unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
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unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
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&ARM::DPRRegClass);
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if (DReg != ARM::NoRegister) return ARM::ssub_1;
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return ARM::ssub_0;
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}
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// Get the subreg type that is most likely to be coalesced
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// for an SPR register that will be used in VDUP32d pseudo.
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unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
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if (!TRI->isVirtualRegister(SReg))
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return getDPRLaneFromSPR(SReg);
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MachineInstr *MI = MRI->getVRegDef(SReg);
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if (!MI) return ARM::ssub_0;
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MachineOperand *MO = MI->findRegisterDefOperand(SReg);
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assert(MO->isReg() && "Non register operand found!");
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if (!MO) return ARM::ssub_0;
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if (MI->isCopy() && usesRegClass(MI->getOperand(1),
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&ARM::SPRRegClass)) {
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SReg = MI->getOperand(1).getReg();
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}
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if (TargetRegisterInfo::isVirtualRegister(SReg)) {
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if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
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return ARM::ssub_0;
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}
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return getDPRLaneFromSPR(SReg);
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}
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// MI is known to be dead. Figure out what instructions
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// are also made dead by this and mark them for removal.
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void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
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SmallVector<MachineInstr *, 8> Front;
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DeadInstr.insert(MI);
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DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
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Front.push_back(MI);
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while (Front.size() != 0) {
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MI = Front.back();
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Front.pop_back();
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// MI is already known to be dead. We need to see
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// if other instructions can also be removed.
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for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if ((!MO.isReg()) || (!MO.isUse()))
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continue;
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unsigned Reg = MO.getReg();
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if (!TRI->isVirtualRegister(Reg))
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continue;
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MachineOperand *Op = MI->findRegisterDefOperand(Reg);
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if (!Op)
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continue;
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MachineInstr *Def = Op->getParent();
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// We don't need to do anything if we have already marked
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// this instruction as being dead.
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if (DeadInstr.find(Def) != DeadInstr.end())
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continue;
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// Check if all the uses of this instruction are marked as
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// dead. If so, we can also mark this instruction as being
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// dead.
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bool IsDead = true;
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for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
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MachineOperand &MODef = Def->getOperand(j);
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if ((!MODef.isReg()) || (!MODef.isDef()))
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continue;
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unsigned DefReg = MODef.getReg();
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if (!TRI->isVirtualRegister(DefReg)) {
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IsDead = false;
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break;
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}
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for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg),
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EE = MRI->use_end();
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II != EE; ++II) {
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// We don't care about self references.
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if (&*II == Def)
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continue;
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if (DeadInstr.find(&*II) == DeadInstr.end()) {
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IsDead = false;
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break;
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}
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}
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}
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if (!IsDead) continue;
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DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
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DeadInstr.insert(Def);
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}
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}
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}
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// Creates the more optimized patterns and generally does all the code
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// transformations in this pass.
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unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
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if (MI->isCopy()) {
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return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
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}
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if (MI->isInsertSubreg()) {
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unsigned DPRReg = MI->getOperand(1).getReg();
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unsigned SPRReg = MI->getOperand(2).getReg();
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if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
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MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
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MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
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if (DPRMI && SPRMI) {
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// See if the first operand of this insert_subreg is IMPLICIT_DEF
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MachineInstr *ECDef = elideCopies(DPRMI);
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if (ECDef != 0 && ECDef->isImplicitDef()) {
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// Another corner case - if we're inserting something that is purely
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// a subreg copy of a DPR, just use that DPR.
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MachineInstr *EC = elideCopies(SPRMI);
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// Is it a subreg copy of ssub_0?
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if (EC && EC->isCopy() &&
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EC->getOperand(1).getSubReg() == ARM::ssub_0) {
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DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
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// Find the thing we're subreg copying out of - is it of the same
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// regclass as DPRMI? (i.e. a DPR or QPR).
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unsigned FullReg = SPRMI->getOperand(1).getReg();
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const TargetRegisterClass *TRC =
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MRI->getRegClass(MI->getOperand(1).getReg());
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if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
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DEBUG(dbgs() << "Subreg copy is compatible - returning ");
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DEBUG(dbgs() << PrintReg(FullReg) << "\n");
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eraseInstrWithNoUses(MI);
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return FullReg;
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}
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}
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return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
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}
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}
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}
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return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
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}
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if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
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&ARM::SPRRegClass)) {
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// See if all bar one of the operands are IMPLICIT_DEF and insert the
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// optimizer pattern accordingly.
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unsigned NumImplicit = 0, NumTotal = 0;
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unsigned NonImplicitReg = ~0U;
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for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
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if (!MI->getOperand(I).isReg())
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continue;
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++NumTotal;
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unsigned OpReg = MI->getOperand(I).getReg();
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if (!TRI->isVirtualRegister(OpReg))
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break;
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MachineInstr *Def = MRI->getVRegDef(OpReg);
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if (!Def)
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break;
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if (Def->isImplicitDef())
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++NumImplicit;
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else
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NonImplicitReg = MI->getOperand(I).getReg();
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}
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if (NumImplicit == NumTotal - 1)
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return optimizeAllLanesPattern(MI, NonImplicitReg);
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else
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return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
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}
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assert(0 && "Unhandled update pattern!");
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return 0;
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}
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// Return true if this MachineInstr inserts a scalar (SPR) value into
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// a D or Q register.
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bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
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// The only way we can do a partial register update is through a COPY,
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// INSERT_SUBREG or REG_SEQUENCE.
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if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
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return true;
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if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
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&ARM::SPRRegClass))
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return true;
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if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
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return true;
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return false;
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}
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// Looks through full copies to get the instruction that defines the input
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// operand for MI.
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MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
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if (!MI->isFullCopy())
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return MI;
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if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
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return NULL;
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MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
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if (!Def)
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return NULL;
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return elideCopies(Def);
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}
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// Look through full copies and PHIs to get the set of non-copy MachineInstrs
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// that can produce MI.
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void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
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SmallVectorImpl<MachineInstr*> &Outs) {
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// Looking through PHIs may create loops so we need to track what
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// instructions we have visited before.
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std::set<MachineInstr *> Reached;
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SmallVector<MachineInstr *, 8> Front;
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Front.push_back(MI);
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while (Front.size() != 0) {
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MI = Front.back();
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Front.pop_back();
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// If we have already explored this MachineInstr, ignore it.
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if (Reached.find(MI) != Reached.end())
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continue;
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Reached.insert(MI);
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if (MI->isPHI()) {
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for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
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unsigned Reg = MI->getOperand(I).getReg();
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if (!TRI->isVirtualRegister(Reg)) {
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continue;
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}
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MachineInstr *NewMI = MRI->getVRegDef(Reg);
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if (!NewMI)
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continue;
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Front.push_back(NewMI);
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}
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} else if (MI->isFullCopy()) {
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if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
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continue;
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MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
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if (!NewMI)
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continue;
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Front.push_back(NewMI);
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} else {
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DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
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Outs.push_back(MI);
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}
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}
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}
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// Return the DPR virtual registers that are read by this machine instruction
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// (if any).
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SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
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if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
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MI->isKill())
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return SmallVector<unsigned, 8>();
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SmallVector<unsigned, 8> Defs;
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for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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if (!usesRegClass(MO, &ARM::DPRRegClass) &&
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!usesRegClass(MO, &ARM::QPRRegClass))
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continue;
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Defs.push_back(MO.getReg());
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}
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return Defs;
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}
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// Creates a DPR register from an SPR one by using a VDUP.
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unsigned
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A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned Reg, unsigned Lane, bool QPR) {
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unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
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&ARM::DPRRegClass);
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AddDefaultPred(BuildMI(MBB,
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InsertBefore,
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DL,
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TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
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Out)
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.addReg(Reg)
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.addImm(Lane));
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return Out;
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}
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// Creates a SPR register from a DPR by copying the value in lane 0.
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unsigned
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A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned DReg, unsigned Lane,
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const TargetRegisterClass *TRC) {
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unsigned Out = MRI->createVirtualRegister(TRC);
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BuildMI(MBB,
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InsertBefore,
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DL,
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TII->get(TargetOpcode::COPY), Out)
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.addReg(DReg, 0, Lane);
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return Out;
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}
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// Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
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unsigned
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A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned Reg1, unsigned Reg2) {
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unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
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BuildMI(MBB,
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InsertBefore,
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DL,
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TII->get(TargetOpcode::REG_SEQUENCE), Out)
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.addReg(Reg1)
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.addImm(ARM::dsub_0)
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.addReg(Reg2)
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.addImm(ARM::dsub_1);
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return Out;
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}
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// Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
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// and merges them into one DPR register.
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unsigned
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A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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DebugLoc DL,
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unsigned Ssub0, unsigned Ssub1) {
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unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
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AddDefaultPred(BuildMI(MBB,
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InsertBefore,
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DL,
|
|
TII->get(ARM::VEXTd32), Out)
|
|
.addReg(Ssub0)
|
|
.addReg(Ssub1)
|
|
.addImm(1));
|
|
return Out;
|
|
}
|
|
|
|
unsigned
|
|
A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator InsertBefore,
|
|
DebugLoc DL, unsigned DReg, unsigned Lane,
|
|
unsigned ToInsert) {
|
|
unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
|
|
BuildMI(MBB,
|
|
InsertBefore,
|
|
DL,
|
|
TII->get(TargetOpcode::INSERT_SUBREG), Out)
|
|
.addReg(DReg)
|
|
.addReg(ToInsert)
|
|
.addImm(Lane);
|
|
|
|
return Out;
|
|
}
|
|
|
|
unsigned
|
|
A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator InsertBefore,
|
|
DebugLoc DL) {
|
|
unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
|
|
BuildMI(MBB,
|
|
InsertBefore,
|
|
DL,
|
|
TII->get(TargetOpcode::IMPLICIT_DEF), Out);
|
|
return Out;
|
|
}
|
|
|
|
// This function inserts instructions in order to optimize interactions between
|
|
// SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
|
|
// lanes, and the using VEXT instructions to recompose the result.
|
|
unsigned
|
|
A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
|
|
MachineBasicBlock::iterator InsertPt(MI);
|
|
DebugLoc DL = MI->getDebugLoc();
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
InsertPt++;
|
|
unsigned Out;
|
|
|
|
if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass)) {
|
|
unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
|
|
ARM::dsub_0, &ARM::DPRRegClass);
|
|
unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
|
|
ARM::dsub_1, &ARM::DPRRegClass);
|
|
|
|
unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
|
|
unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
|
|
Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
|
|
|
|
unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
|
|
unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
|
|
Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
|
|
|
|
Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
|
|
|
|
} else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
|
|
unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
|
|
unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
|
|
Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
|
|
|
|
} else {
|
|
assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
|
|
"Found unexpected regclass!");
|
|
|
|
unsigned PrefLane = getPrefSPRLane(Reg);
|
|
unsigned Lane;
|
|
switch (PrefLane) {
|
|
case ARM::ssub_0: Lane = 0; break;
|
|
case ARM::ssub_1: Lane = 1; break;
|
|
default: llvm_unreachable("Unknown preferred lane!");
|
|
}
|
|
|
|
bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass);
|
|
|
|
Out = createImplicitDef(MBB, InsertPt, DL);
|
|
Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
|
|
Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
|
|
eraseInstrWithNoUses(MI);
|
|
}
|
|
return Out;
|
|
}
|
|
|
|
bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
|
|
// We look for instructions that write S registers that are then read as
|
|
// D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
|
|
// REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
|
|
// merge two SPR values to form a DPR register. In order avoid false
|
|
// positives we make sure that there is an SPR producer so we look past
|
|
// COPY and PHI nodes to find it.
|
|
//
|
|
// The best code pattern for when an SPR producer is going to be used by a
|
|
// DPR or QPR consumer depends on whether the other lanes of the
|
|
// corresponding DPR/QPR are currently defined.
|
|
//
|
|
// We can handle these efficiently, depending on the type of
|
|
// pseudo-instruction that is producing the pattern
|
|
//
|
|
// * COPY: * VDUP all lanes and merge the results together
|
|
// using VEXTs.
|
|
//
|
|
// * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
|
|
// lane, and the other lane(s) of the DPR/QPR register
|
|
// that we are inserting in are undefined, use the
|
|
// original DPR/QPR value.
|
|
// * Otherwise, fall back on the same stategy as COPY.
|
|
//
|
|
// * REG_SEQUENCE: * If all except one of the input operands are
|
|
// IMPLICIT_DEFs, insert the VDUP pattern for just the
|
|
// defined input operand
|
|
// * Otherwise, fall back on the same stategy as COPY.
|
|
//
|
|
|
|
// First, get all the reads of D-registers done by this instruction.
|
|
SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
|
|
bool Modified = false;
|
|
|
|
for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
|
|
I != E; ++I) {
|
|
// Follow the def-use chain for this DPR through COPYs, and also through
|
|
// PHIs (which are essentially multi-way COPYs). It is because of PHIs that
|
|
// we can end up with multiple defs of this DPR.
|
|
|
|
SmallVector<MachineInstr *, 8> DefSrcs;
|
|
if (!TRI->isVirtualRegister(*I))
|
|
continue;
|
|
MachineInstr *Def = MRI->getVRegDef(*I);
|
|
if (!Def)
|
|
continue;
|
|
|
|
elideCopiesAndPHIs(Def, DefSrcs);
|
|
|
|
for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
|
|
EE = DefSrcs.end(); II != EE; ++II) {
|
|
MachineInstr *MI = *II;
|
|
|
|
// If we've already analyzed and replaced this operand, don't do
|
|
// anything.
|
|
if (Replacements.find(MI) != Replacements.end())
|
|
continue;
|
|
|
|
// Now, work out if the instruction causes a SPR->DPR dependency.
|
|
if (!hasPartialWrite(MI))
|
|
continue;
|
|
|
|
// Collect all the uses of this MI's DPR def for updating later.
|
|
SmallVector<MachineOperand*, 8> Uses;
|
|
unsigned DPRDefReg = MI->getOperand(0).getReg();
|
|
for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
|
|
E = MRI->use_end(); I != E; ++I)
|
|
Uses.push_back(&I.getOperand());
|
|
|
|
// We can optimize this.
|
|
unsigned NewReg = optimizeSDPattern(MI);
|
|
|
|
if (NewReg != 0) {
|
|
Modified = true;
|
|
for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
|
|
E = Uses.end(); I != E; ++I) {
|
|
// Make sure to constrain the register class of the new register to
|
|
// match what we're replacing. Otherwise we can optimize a DPR_VFP2
|
|
// reference into a plain DPR, and that will end poorly. NewReg is
|
|
// always virtual here, so there will always be a matching subclass
|
|
// to find.
|
|
MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
|
|
|
|
DEBUG(dbgs() << "Replacing operand "
|
|
<< **I << " with "
|
|
<< PrintReg(NewReg) << "\n");
|
|
(*I)->substVirtReg(NewReg, 0, *TRI);
|
|
}
|
|
}
|
|
Replacements[MI] = NewReg;
|
|
}
|
|
}
|
|
return Modified;
|
|
}
|
|
|
|
bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
|
|
TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
|
|
TRI = Fn.getTarget().getRegisterInfo();
|
|
MRI = &Fn.getRegInfo();
|
|
bool Modified = false;
|
|
|
|
DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
|
|
|
|
DeadInstr.clear();
|
|
Replacements.clear();
|
|
|
|
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
|
|
++MFI) {
|
|
|
|
for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
|
|
MI != ME;) {
|
|
Modified |= runOnInstruction(MI++);
|
|
}
|
|
|
|
}
|
|
|
|
for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
|
|
E = DeadInstr.end();
|
|
I != E; ++I) {
|
|
(*I)->eraseFromParent();
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
FunctionPass *llvm::createA15SDOptimizerPass() {
|
|
return new A15SDOptimizer();
|
|
}
|