mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
3e99b715d1
X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
274 lines
8.8 KiB
TableGen
274 lines
8.8 KiB
TableGen
//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for X86
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def IIC_DEFAULT : InstrItinClass;
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def IIC_ALU_MEM : InstrItinClass;
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def IIC_ALU_NONMEM : InstrItinClass;
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def IIC_LEA : InstrItinClass;
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def IIC_LEA_16 : InstrItinClass;
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def IIC_MUL8 : InstrItinClass;
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def IIC_MUL16_MEM : InstrItinClass;
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def IIC_MUL16_REG : InstrItinClass;
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def IIC_MUL32_MEM : InstrItinClass;
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def IIC_MUL32_REG : InstrItinClass;
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def IIC_MUL64 : InstrItinClass;
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// imul by al, ax, eax, tax
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def IIC_IMUL8 : InstrItinClass;
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def IIC_IMUL16_MEM : InstrItinClass;
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def IIC_IMUL16_REG : InstrItinClass;
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def IIC_IMUL32_MEM : InstrItinClass;
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def IIC_IMUL32_REG : InstrItinClass;
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def IIC_IMUL64 : InstrItinClass;
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// imul reg by reg|mem
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def IIC_IMUL16_RM : InstrItinClass;
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def IIC_IMUL16_RR : InstrItinClass;
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def IIC_IMUL32_RM : InstrItinClass;
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def IIC_IMUL32_RR : InstrItinClass;
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def IIC_IMUL64_RM : InstrItinClass;
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def IIC_IMUL64_RR : InstrItinClass;
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// imul reg = reg/mem * imm
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def IIC_IMUL16_RMI : InstrItinClass;
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def IIC_IMUL16_RRI : InstrItinClass;
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def IIC_IMUL32_RMI : InstrItinClass;
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def IIC_IMUL32_RRI : InstrItinClass;
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def IIC_IMUL64_RMI : InstrItinClass;
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def IIC_IMUL64_RRI : InstrItinClass;
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// div
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def IIC_DIV8_MEM : InstrItinClass;
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def IIC_DIV8_REG : InstrItinClass;
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def IIC_DIV16 : InstrItinClass;
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def IIC_DIV32 : InstrItinClass;
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def IIC_DIV64 : InstrItinClass;
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// idiv
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def IIC_IDIV8 : InstrItinClass;
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def IIC_IDIV16 : InstrItinClass;
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def IIC_IDIV32 : InstrItinClass;
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def IIC_IDIV64 : InstrItinClass;
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// neg/not/inc/dec
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def IIC_UNARY_REG : InstrItinClass;
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def IIC_UNARY_MEM : InstrItinClass;
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// add/sub/and/or/xor/adc/sbc/cmp/test
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def IIC_BIN_MEM : InstrItinClass;
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def IIC_BIN_NONMEM : InstrItinClass;
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// shift/rotate
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def IIC_SR : InstrItinClass;
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// shift double
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def IIC_SHD16_REG_IM : InstrItinClass;
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def IIC_SHD16_REG_CL : InstrItinClass;
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def IIC_SHD16_MEM_IM : InstrItinClass;
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def IIC_SHD16_MEM_CL : InstrItinClass;
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def IIC_SHD32_REG_IM : InstrItinClass;
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def IIC_SHD32_REG_CL : InstrItinClass;
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def IIC_SHD32_MEM_IM : InstrItinClass;
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def IIC_SHD32_MEM_CL : InstrItinClass;
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def IIC_SHD64_REG_IM : InstrItinClass;
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def IIC_SHD64_REG_CL : InstrItinClass;
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def IIC_SHD64_MEM_IM : InstrItinClass;
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def IIC_SHD64_MEM_CL : InstrItinClass;
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// cmov
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def IIC_CMOV16_RM : InstrItinClass;
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def IIC_CMOV16_RR : InstrItinClass;
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def IIC_CMOV32_RM : InstrItinClass;
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def IIC_CMOV32_RR : InstrItinClass;
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def IIC_CMOV64_RM : InstrItinClass;
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def IIC_CMOV64_RR : InstrItinClass;
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// set
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def IIC_SET_R : InstrItinClass;
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def IIC_SET_M : InstrItinClass;
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// jmp/jcc/jcxz
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def IIC_Jcc : InstrItinClass;
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def IIC_JCXZ : InstrItinClass;
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def IIC_JMP_REL : InstrItinClass;
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def IIC_JMP_REG : InstrItinClass;
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def IIC_JMP_MEM : InstrItinClass;
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def IIC_JMP_FAR_MEM : InstrItinClass;
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def IIC_JMP_FAR_PTR : InstrItinClass;
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// loop
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def IIC_LOOP : InstrItinClass;
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def IIC_LOOPE : InstrItinClass;
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def IIC_LOOPNE : InstrItinClass;
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// call
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def IIC_CALL_RI : InstrItinClass;
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def IIC_CALL_MEM : InstrItinClass;
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def IIC_CALL_FAR_MEM : InstrItinClass;
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def IIC_CALL_FAR_PTR : InstrItinClass;
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// ret
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def IIC_RET : InstrItinClass;
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def IIC_RET_IMM : InstrItinClass;
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//sign extension movs
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def IIC_MOVSX : InstrItinClass;
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def IIC_MOVSX_R16_R8 : InstrItinClass;
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def IIC_MOVSX_R16_M8 : InstrItinClass;
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def IIC_MOVSX_R16_R16 : InstrItinClass;
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def IIC_MOVSX_R32_R32 : InstrItinClass;
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//zero extension movs
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def IIC_MOVZX : InstrItinClass;
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def IIC_MOVZX_R16_R8 : InstrItinClass;
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def IIC_MOVZX_R16_M8 : InstrItinClass;
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def IIC_REP_MOVS : InstrItinClass;
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def IIC_REP_STOS : InstrItinClass;
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// SSE scalar/parallel binary operations
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def IIC_SSE_ALU_F32S_RR : InstrItinClass;
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def IIC_SSE_ALU_F32S_RM : InstrItinClass;
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def IIC_SSE_ALU_F64S_RR : InstrItinClass;
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def IIC_SSE_ALU_F64S_RM : InstrItinClass;
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def IIC_SSE_MUL_F32S_RR : InstrItinClass;
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def IIC_SSE_MUL_F32S_RM : InstrItinClass;
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def IIC_SSE_MUL_F64S_RR : InstrItinClass;
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def IIC_SSE_MUL_F64S_RM : InstrItinClass;
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def IIC_SSE_DIV_F32S_RR : InstrItinClass;
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def IIC_SSE_DIV_F32S_RM : InstrItinClass;
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def IIC_SSE_DIV_F64S_RR : InstrItinClass;
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def IIC_SSE_DIV_F64S_RM : InstrItinClass;
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def IIC_SSE_ALU_F32P_RR : InstrItinClass;
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def IIC_SSE_ALU_F32P_RM : InstrItinClass;
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def IIC_SSE_ALU_F64P_RR : InstrItinClass;
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def IIC_SSE_ALU_F64P_RM : InstrItinClass;
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def IIC_SSE_MUL_F32P_RR : InstrItinClass;
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def IIC_SSE_MUL_F32P_RM : InstrItinClass;
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def IIC_SSE_MUL_F64P_RR : InstrItinClass;
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def IIC_SSE_MUL_F64P_RM : InstrItinClass;
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def IIC_SSE_DIV_F32P_RR : InstrItinClass;
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def IIC_SSE_DIV_F32P_RM : InstrItinClass;
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def IIC_SSE_DIV_F64P_RR : InstrItinClass;
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def IIC_SSE_DIV_F64P_RM : InstrItinClass;
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def IIC_SSE_COMIS_RR : InstrItinClass;
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def IIC_SSE_COMIS_RM : InstrItinClass;
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def IIC_SSE_HADDSUB_RR : InstrItinClass;
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def IIC_SSE_HADDSUB_RM : InstrItinClass;
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def IIC_SSE_BIT_P_RR : InstrItinClass;
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def IIC_SSE_BIT_P_RM : InstrItinClass;
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def IIC_SSE_INTALU_P_RR : InstrItinClass;
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def IIC_SSE_INTALU_P_RM : InstrItinClass;
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def IIC_SSE_INTALUQ_P_RR : InstrItinClass;
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def IIC_SSE_INTALUQ_P_RM : InstrItinClass;
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def IIC_SSE_INTMUL_P_RR : InstrItinClass;
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def IIC_SSE_INTMUL_P_RM : InstrItinClass;
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def IIC_SSE_INTSH_P_RR : InstrItinClass;
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def IIC_SSE_INTSH_P_RM : InstrItinClass;
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def IIC_SSE_INTSH_P_RI : InstrItinClass;
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def IIC_SSE_CMPP_RR : InstrItinClass;
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def IIC_SSE_CMPP_RM : InstrItinClass;
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def IIC_SSE_SHUFP : InstrItinClass;
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def IIC_SSE_PSHUF : InstrItinClass;
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def IIC_SSE_UNPCK : InstrItinClass;
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def IIC_SSE_MOVMSK : InstrItinClass;
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def IIC_SSE_MASKMOV : InstrItinClass;
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def IIC_SSE_PEXTRW : InstrItinClass;
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def IIC_SSE_PINSRW : InstrItinClass;
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def IIC_SSE_PABS_RR : InstrItinClass;
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def IIC_SSE_PABS_RM : InstrItinClass;
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def IIC_SSE_SQRTP_RR : InstrItinClass;
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def IIC_SSE_SQRTP_RM : InstrItinClass;
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def IIC_SSE_SQRTS_RR : InstrItinClass;
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def IIC_SSE_SQRTS_RM : InstrItinClass;
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def IIC_SSE_RCPP_RR : InstrItinClass;
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def IIC_SSE_RCPP_RM : InstrItinClass;
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def IIC_SSE_RCPS_RR : InstrItinClass;
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def IIC_SSE_RCPS_RM : InstrItinClass;
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def IIC_SSE_MOV_S_RR : InstrItinClass;
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def IIC_SSE_MOV_S_RM : InstrItinClass;
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def IIC_SSE_MOV_S_MR : InstrItinClass;
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def IIC_SSE_MOVA_P_RR : InstrItinClass;
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def IIC_SSE_MOVA_P_RM : InstrItinClass;
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def IIC_SSE_MOVA_P_MR : InstrItinClass;
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def IIC_SSE_MOVU_P_RR : InstrItinClass;
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def IIC_SSE_MOVU_P_RM : InstrItinClass;
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def IIC_SSE_MOVU_P_MR : InstrItinClass;
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def IIC_SSE_MOVDQ : InstrItinClass;
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def IIC_SSE_MOVD_ToGP : InstrItinClass;
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def IIC_SSE_MOVQ_RR : InstrItinClass;
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def IIC_SSE_MOV_LH : InstrItinClass;
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def IIC_SSE_LDDQU : InstrItinClass;
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def IIC_SSE_MOVNT : InstrItinClass;
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def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
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def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
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def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
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def IIC_SSE_PSHUFB_RR : InstrItinClass;
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def IIC_SSE_PSHUFB_RM : InstrItinClass;
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def IIC_SSE_PSIGN_RR : InstrItinClass;
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def IIC_SSE_PSIGN_RM : InstrItinClass;
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def IIC_SSE_PMADD : InstrItinClass;
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def IIC_SSE_PMULHRSW : InstrItinClass;
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def IIC_SSE_PALIGNR : InstrItinClass;
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def IIC_SSE_MWAIT : InstrItinClass;
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def IIC_SSE_MONITOR : InstrItinClass;
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def IIC_SSE_PREFETCH : InstrItinClass;
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def IIC_SSE_PAUSE : InstrItinClass;
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def IIC_SSE_LFENCE : InstrItinClass;
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def IIC_SSE_MFENCE : InstrItinClass;
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def IIC_SSE_SFENCE : InstrItinClass;
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def IIC_SSE_LDMXCSR : InstrItinClass;
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def IIC_SSE_STMXCSR : InstrItinClass;
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def IIC_SSE_CVT_PD_RR : InstrItinClass;
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def IIC_SSE_CVT_PD_RM : InstrItinClass;
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def IIC_SSE_CVT_PS_RR : InstrItinClass;
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def IIC_SSE_CVT_PS_RM : InstrItinClass;
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def IIC_SSE_CVT_PI2PS_RR : InstrItinClass;
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def IIC_SSE_CVT_PI2PS_RM : InstrItinClass;
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def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
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def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
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def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
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def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
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def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
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def IIC_CMPX_LOCK : InstrItinClass;
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def IIC_CMPX_LOCK_8 : InstrItinClass;
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def IIC_CMPX_LOCK_8B : InstrItinClass;
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def IIC_CMPX_LOCK_16B : InstrItinClass;
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def IIC_XADD_LOCK_MEM : InstrItinClass;
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def IIC_XADD_LOCK_MEM8 : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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def GenericItineraries : ProcessorItineraries<[], [], []>;
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include "X86ScheduleAtom.td"
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