llvm-6502/test/CodeGen/ARM/fixunsdfdi.ll
Dan Gohman ae3a0be92e Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04 22:49:04 +00:00

30 lines
861 B
LLVM

; RUN: llvm-as < %s | llc -march=arm -mattr=+vfp2
; RUN: llvm-as < %s | llc -march=arm -mattr=vfp2 | not grep fstd
define hidden i64 @__fixunsdfdi(double %x) nounwind readnone {
entry:
%x14 = bitcast double %x to i64 ; <i64> [#uses=1]
br i1 true, label %bb3, label %bb10
bb3: ; preds = %entry
br i1 true, label %bb5, label %bb7
bb5: ; preds = %bb3
%u.in.mask = and i64 %x14, -4294967296 ; <i64> [#uses=1]
%.ins = or i64 0, %u.in.mask ; <i64> [#uses=1]
%0 = bitcast i64 %.ins to double ; <double> [#uses=1]
%1 = fsub double %x, %0 ; <double> [#uses=1]
%2 = fptosi double %1 to i32 ; <i32> [#uses=1]
%3 = add i32 %2, 0 ; <i32> [#uses=1]
%4 = zext i32 %3 to i64 ; <i64> [#uses=1]
%5 = shl i64 %4, 32 ; <i64> [#uses=1]
%6 = or i64 %5, 0 ; <i64> [#uses=1]
ret i64 %6
bb7: ; preds = %bb3
ret i64 0
bb10: ; preds = %entry
ret i64 0
}