mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Currently, we canonicalize shuffles that produce a result larger than their operands with: shuffle(concat(v1, undef), concat(v2, undef)) -> shuffle(concat(v1, v2), undef) because we can access quad vectors (see PerformVECTOR_SHUFFLECombine). This is useful in the general case, but there are special cases where native shuffles produce larger results: the two-result ops. We can look through the concat when lowering them: shuffle(concat(v1, v2), undef) -> concat(VZIP(v1, v2):0, :1) This lets us generate the native shuffles instead of scalarizing to dozens of VMOVs. Differential Revision: http://reviews.llvm.org/D10424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240118 91177308-0d34-0410-b5e6-96231b3b80d8
328 lines
13 KiB
LLVM
328 lines
13 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrni8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vtrn.8 d17, d16
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; CHECK-NEXT: vadd.i8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrni8_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vtrni16:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vtrn.16 d17, d16
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; CHECK-NEXT: vadd.i16 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vtrni16_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.16 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
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ret <8 x i16> %tmp3
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}
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define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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; CHECK-LABEL: vtrni32:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vtrn.32 d17, d16
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; CHECK-NEXT: vadd.i32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = add <2 x i32> %tmp3, %tmp4
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ret <2 x i32> %tmp5
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}
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define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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; CHECK-LABEL: vtrni32_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.32 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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ret <4 x i32> %tmp3
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}
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define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vtrnf:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vtrn.32 d17, d16
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; CHECK-NEXT: vadd.f32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = fadd <2 x float> %tmp3, %tmp4
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ret <2 x float> %tmp5
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}
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define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vtrnf_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.32 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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ret <4 x float> %tmp3
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}
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define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrnQi8:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vtrn.8 q9, q8
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; CHECK-NEXT: vadd.i8 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrnQi8_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vtrn.8 q9, q8
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; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30, i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
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ret <32 x i8> %tmp3
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}
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define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vtrnQi16:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vtrn.16 q9, q8
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; CHECK-NEXT: vadd.i16 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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; CHECK-LABEL: vtrnQi16_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vtrn.16 q9, q8
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; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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ret <16 x i16> %tmp3
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}
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define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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; CHECK-LABEL: vtrnQi32:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vtrn.32 q9, q8
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; CHECK-NEXT: vadd.i32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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; CHECK-LABEL: vtrnQi32_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vtrn.32 q9, q8
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; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
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ret <8 x i32> %tmp3
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}
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define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vtrnQf:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vtrn.32 q9, q8
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; CHECK-NEXT: vadd.f32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
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; CHECK-LABEL: vtrnQf_QQres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
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; CHECK-NEXT: vtrn.32 q9, q8
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; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
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; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 4, i32 2, i32 6, i32 1, i32 5, i32 3, i32 7>
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ret <8 x float> %tmp3
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}
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define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrni8_undef:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vtrn.8 d17, d16
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; CHECK-NEXT: vadd.i8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vtrni8_undef_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vtrn.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14, i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
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|
ret <16 x i8> %tmp3
|
|
}
|
|
|
|
define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
|
; CHECK-LABEL: vtrnQi16_undef:
|
|
; CHECK: @ BB#0:
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|
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
|
|
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
|
|
; CHECK-NEXT: vtrn.16 q9, q8
|
|
; CHECK-NEXT: vadd.i16 q8, q9, q8
|
|
; CHECK-NEXT: vmov r0, r1, d16
|
|
; CHECK-NEXT: vmov r2, r3, d17
|
|
; CHECK-NEXT: mov pc, lr
|
|
%tmp1 = load <8 x i16>, <8 x i16>* %A
|
|
%tmp2 = load <8 x i16>, <8 x i16>* %B
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
|
|
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
|
|
%tmp5 = add <8 x i16> %tmp3, %tmp4
|
|
ret <8 x i16> %tmp5
|
|
}
|
|
|
|
define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
|
; CHECK-LABEL: vtrnQi16_undef_QQres:
|
|
; CHECK: @ BB#0:
|
|
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
|
|
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
|
|
; CHECK-NEXT: vtrn.16 q9, q8
|
|
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
|
|
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
|
|
; CHECK-NEXT: mov pc, lr
|
|
%tmp1 = load <8 x i16>, <8 x i16>* %A
|
|
%tmp2 = load <8 x i16>, <8 x i16>* %B
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14, i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
|
|
ret <16 x i16> %tmp3
|
|
}
|