cache disassemblers according to the string value
of the target triple, not according to the enum
of the triple CPU. The reason for this is that
certain attributes of the instruction set are not
reflected in the enum, but only in the string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149773 91177308-0d34-0410-b5e6-96231b3b80d8